A dielectric film containing Zr—Sn—Ti—O formed by atomic layer deposition using a TiI4 precursor and a method of fabricating such a dielectric film produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Depositing titanium and oxygen onto a substrate surface by atomic layer deposition using a TiI4 precursor, depositing zirconium and oxygen onto a substrate surface by atomic layer deposition, and depositing tin and oxygen onto a substrate surface by atomic layer deposition form the Zr—Sn—Ti—O dielectric layer. Dielectric films containing Zr—Sn—Ti—O formed by atomic layer deposition using TiI4 are thermodynamically stable such that the Zr—Sn—Ti—O will have minimal reactions with a silicon substrate or other structures during processing.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An electronic device comprising: a substrate; and a dielectric layer on the substrate, the dielectric layer containing a Zr—Sn—Ti—O layer, the Zr—Sn—Ti—O layer having a surface with a roughness less than a monolayer of the Zr—Sn—Ti—O, the Zr—Sn—Ti—O layer substantially chlorine free.
2. The electronic device of claim 1 , wherein the Zr—Sn—Ti—O layer includes an amorphous Ti-rich Zr—Sn—Ti—O film.
3. The electronic device of claim 1 , wherein the Zr—Sn—Ti—O layer includes a dielectric film having a composition substantially of Zr y Sn x Ti 1-x-y O 4 with 0.3<y<0.7 and 0<x<0.2.
4. The electronic device of claim 1 , wherein the Zr—Sn—Ti—O layer includes a dielectric film having a composition substantially of Zr 0.2 Sn 0.2 Ti 0.6 O 2 .
5. The electronic device of claim 1 , wherein the dielectric layer is a dielectric material of a capacitor in the electronic device.
6. The electronic device of claim 1 , wherein the dielectric layer is a gate dielectric of a transistor in the electronic device.
7. The electronic device of claim 1 , wherein the dielectric layer is a gate dielectric disposed in a memory of the electronic device.
8. The electronic device of claim 1 , wherein the electronic device is adapted into an electronic system.
9. A capacitor, comprising: a first conductive layer on a substrate; a dielectric layer containing a Zr—Sn—Ti—O layer, the Zr—Sn—Ti—O layer having a surface with a roughness less than a monolayer of the Zr—Sn—Ti—O, the Zr—Sn—Ti—O layer substantially chlorine free; and a second conductive layer disposed on the dielectric layer.
10. The capacitor of claim 9 , wherein the dielectric layer exhibits a dielectric constant in the range from about 50 to about 70.
11. The capacitor of claim 9 , wherein the Zr—Sn—Ti—O layer includes an amorphous Ti-rich Zr—Sn—Ti—O film.
12. A transistor comprising: a body region on a substrate between a source region and a drain region; a dielectric film containing a Zr—Sn—Ti—O layer, the Zr—Sn—Ti—O layer having a surface with a roughness less than a monolayer of the Zr—Sn—Ti—O, the Zr—Sn—Ti—O layer substantially chlorine free, the Zr—Sn—Ti—O layer including a solid solution of titanium oxide, zirconium oxide, and tin oxide, the dielectric film disposed on the body region between the source region and the drain region; and a gate coupled to the dielectric film.
13. The transistor of claim 12 , wherein the dielectric film is substantially amorphous.
14. The transistor of claim 12 , wherein the dielectric film exhibits a dielectric constant in the range from about 50 to about 70.
15. The transistor of claim 12 , wherein the dielectric film exhibits an equivalent oxide thickness (t eq ) less than about 10 Angstroms.
16. The transistor of claim 12 , wherein the dielectric film exhibits an equivalent oxide thickness (t eq ) of less than about 3 Angstroms.
17. The transistor of claim 12 , wherein the Zr—Sn—Ti—O layer is substantially Ti-rich.
18. A transistor comprising: a body region on a substrate between a source region and a drain region; a gate dielectric disposed on the body region; a floating gate disposed on the gate dielectric; a control gate; a floating gate dielectric interposed between the floating gate and the control gate, wherein at least one of the gate dielectric and the floating gate dielectric includes a dielectric film containing a Zr—Sn—Ti—O layer, the Zr—Sn—Ti—O layer having a surface with a roughness less than a monolayer of the Zr—Sn—Ti—O, the Zr—Sn—Ti—O layer substantially chlorine free.
19. The transistor of claim 18 , wherein the Zr—Sn—Ti—O layer is substantially Ti-rich.
20. The transistor of claim 18 , wherein the dielectric film is substantially amorphous.
21. The transistor of claim 18 , wherein the dielectric film exhibits a dielectric constant in the range from about 50 to about 70.
22. The transistor of claim 18 , wherein the dielectric film exhibits an equivalent oxide thickness (t eq ) less than about 10 Angstroms.
23. The transistor of claim 18 , wherein the dielectric film exhibits an equivalent oxide thickness (t eq ) of less than about 3 Angstroms.
24. A memory comprising: a number of transistors in an array on a substrate, each transistor having a body region between a source region and a drain region, at least one transistor including a gate coupled to a dielectric film disposed above the body region, the dielectric film containing a layer of Zr—Sn—Ti—O, the layer of Zr—Sn—Ti—O having a surface with a roughness less than a monolayer of the Zr—Sn—Ti—O, the layer of Zr—Sn—Ti—O substantially chlorine free; and a number of word lines coupled to a number of the gates of the number of access transistors.
25. The memory of claim 24 , wherein the gate contacts the dielectric film and the dielectric film contacts the body region.
26. The memory of claim 24 , wherein the gate is a floating gate and the dielectric film is interposed between the floating gate and the body region.
27. The memory of claim 24 , wherein the gate is a control gate and the dielectric film is interposed between the control gate and a floating gate.
28. The memory of claim 24 , wherein the dielectric film has a dielectric constant in the range from about 50 to about 70.
29. The memory of claim 24 , wherein the dielectric film has an equivalent oxide thickness (t eq ) less than about 10 Angstroms.
30. An electronic system comprising: a substrate; a dielectric layer on the substrate, the dielectric layer containing a Zr—Sn—Ti—O layer, the Zr—Sn—Ti—O layer having a surface with a roughness less than a monolayer of the Zr—Sn—Ti—O, the Zr—Sn—Ti—O layer substantially chlorine free.
31. The electronic system of claim 30 , wherein the dielectric layer includes an amorphous Ti-rich Zr—Sn—Ti—O film.
32. The electronic system of claim 30 , wherein the dielectric layer includes a dielectric film having a composition substantially of Zr y Sn x Ti 1-x-y O 4 with 0.3<y<0.7 and 0<x<0.2.
33. An electronic system comprising: a processor; a system bus; and a memory coupled to the processor by the system bus, the memory including: a number of transistors in an array on a substrate, each transistor having a body region between a source region and a drain region, at least one transistor including a gate coupled to a dielectric film disposed above the body region, the dielectric film containing a Zr—Sn—Ti—O layer, the Zr—Sn—Ti—O layer having a surface with a roughness less than a monolayer of the Zr—Sn—Ti—O, the Zr—Sn—Ti—O layer substantially chlorine free, wherein the Zr—Sn—Ti—O layer includes a layer of a solid solution of titanium oxide, zirconium oxide, and tin oxide; and a number of word lines coupled to a number of the gates of the number of transistors.
34. The electronic system of claim 33 , wherein the dielectric film has a dielectric constant in the range from about 50 to about 70.
35. The electronic system of claim 33 , wherein the film exhibits an equivalent oxide thickness (t eq ) less than about 10 Angstroms.
36. The electronic system of claim 33 , wherein the Zr—Sn—Ti—O layer is Ti-rich.
37. The electronic system of claim 33 , wherein the memory is a dynamic random access memory.
38. The electronic device of claim 1 , wherein the Zr—Sn—Ti—O layer includes a layer of a solid solution of ZrO 2 , TiO 2 , and SnO 2 .
39. The electronic device of claim 1 , wherein the Zr—Sn—Ti—O layer is substantially without residual iodine.
40. The electronic device of claim 18 , wherein the Zr—Sn—Ti—O layer is substantially without residual iodine.
41. The electronic device of claim 24 , wherein the Zr—Sn—Ti—O layer is substantially without residual iodine.
42. The electronic device of claim 30 , wherein the Zr—Sn—Ti—O layer is substantially without residual iodine.
43. The electronic device of claim 1 , wherein the Zr—Sn—Ti—O layer is structured substantially as a monolayer.
44. The electronic device of claim 1 , wherein the Zr—Sn—Ti—O layer is structured having substantially more than one monolayer of Zr—Sn—Ti—O.
45. The electronic device of claim 9 , wherein the Zr—Sn—Ti—O layer is structured substantially as a monolayer.
46. The electronic device of claim 12 , wherein the Zr—Sn—Ti—O layer is structured substantially as a monolayer.
47. The electronic device of claim 18 , wherein the Zr—Sn—Ti—O layer is structured substantially as a monolayer.
48. The electronic device of claim 18 , wherein the Zr—Sn—Ti—O layer is structured having substantially more than one monolayer of Zr—Sn—Ti—O.
49. The electronic device of claim 24 , wherein the Zr—Sn—Ti—O layer is structured substantially as a monolayer.
50. The electronic device of claim 24 , wherein the Zr—Sn—Ti—O layer is structured having substantially more than one monolayer of Zr—Sn—Ti—O.
51. The electronic device of claim 30 , wherein the Zr—Sn—Ti—O layer is structured substantially as a monolayer.
52. The electronic device of claim 30 , wherein the Zr—Sn—Ti—O layer is structured having substantially more than one monolayer of Zr—Sn—Ti—O.
53. The electronic device of claim 33 , wherein the Zr—Sn—Ti—O layer is structured substantially as a monolayer.
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August 31, 2004
July 22, 2008
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