An electronic memory apparatus has a plurality of memory devices, a plurality of temperature sensors and a control unit. The memory devices each have a multiplicity of nonvolatile memory cells that are refreshed during operation of the electronic memory apparatus. The control unit passes a same periodic clock signal to each of the memory devices. The clock signal causes the memory cells to be refreshed in the memory devices. Each temperature sensor is associated with a respective memory device and measures a local temperature near the respective memory device during operation. Each memory device individually determines, on the basis of the temperature measured by the temperature sensor that is assigned to it, how many of its memory cells are simultaneously refreshed when memory cells are being refreshed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An electronic memory apparatus comprising: a plurality of memory devices each having a plurality of nonvolatile memory cells that are refreshed during operation of the electronic memory apparatus; a control unit coupled to the plurality of memory devices to pass a same periodic clock signal to each of the memory devices, said clock signal causing the memory cells to be refreshed in the memory devices; and a plurality of temperature sensors, each temperature sensor associated with a respective memory device to measure a local temperature near the respective memory device during operation; wherein the plurality of memory devices comprises integrated memory chips that each have a plurality of memory banks, wherein the plurality of memory banks comprise memory cells coupled to word lines in each pulse of the periodic clock signal, wherein based on the measured local temperature, and without changing the frequency of the periodic clock signal, each memory device individually determines a refresh time by changing the number of memory cells simultaneously refreshed, and wherein the number of memory cells simultaneously refreshed is changed by changing the number of word lines simultaneously addressed in each pulse of the clock signal.
2. The memory apparatus as claimed in claim 1 , wherein the memory devices carry out a refresh operation upon each pulse of the periodic clock signal, wherein the number of memory cells that are refreshed during a pulse of the periodic refresh signal is adjustable on the basis of the temperature of the respective memory device.
3. The memory apparatus as claimed in claim 1 , wherein those memory devices whose temperature is outside a prescribed bandwidth for the operating temperature increase or decrease the number of memory cells, which are simultaneously refreshed, by a factor of 2n, n being a natural number.
4. The memory apparatus as claimed in claim 2 , wherein, in each memory device the periodic clock signal is always simultaneously forwarded to all the plurality of memory banks.
5. The memory apparatus as claimed in claim 4 , wherein, when the temperature measured by a temperature sensor assigned to a memory device is within a prescribed bandwidth for the operating temperature, a respective first number of memory cells is simultaneously refreshed in all of the plurality of memory banks of the respective memory device upon each pulse of the periodic clock signal.
6. The memory apparatus as claimed in claim 5 , wherein, when the temperature measured by the temperature sensor assigned to the memory device is above an upper limiting value for the operating temperature, a respective second number of memory cells is simultaneously refreshed in all of the memory banks of the respective memory device upon each pulse of the periodic clock signal, wherein the second number is greater than the first number.
7. The memory apparatus as claimed in claim 6 , wherein, when the temperature measured by a temperature sensor assigned to a memory device is below a lower limiting value for the operating temperature, a third number of memory cells is simultaneously refreshed upon each pulse of the periodic clock signal, wherein the third number is less than the first number, and wherein upon each pulse, the quantity of memory cells refreshed is selected, in a manner encompassing the memory banks, from one or more memory banks of the plurality of memory banks.
8. The memory apparatus as claimed in claim 1 , wherein the memory devices use the periodic clock signal to count and address word lines, wherein the memory cells coupled to respective addressed word lines are refreshed, wherein upon each pulse of the periodic clock signal word lines other than those in the respective preceding pulse of the clock signal are addressed.
9. The memory apparatus as claimed in claim 8 , wherein, when the temperature measured by a temperature sensor assigned to a memory device is within a prescribed bandwidth for the operating temperature, only one word line is addressed in each memory bank upon each pulse of the clock signal, wherein, the word lines of the respective memory bank to be addressed are counted from a first word line to a last word line of the respective memory bank and, wherein, after the last word line of the respective memory bank has been addressed, the first word line of the respective memory bank is addressed again in the next pulse of the clock signal.
10. The memory apparatus as claimed in claim 8 , wherein, when the temperature measured by the temperature sensor associated with the memory device is above an upper limiting value for the operating temperature, 2n word lines are respectively addressed in each memory bank upon each pulse of the clock signal, wherein, n is a natural number and the word lines are counted from a first word line to a last word line, in sub-units of the memory banks and, wherein, after the last word line of the respective sub-unit of the memory bank has been addressed, the first word line of the respective sub-unit of the respective memory bank is addressed again upon the next pulse of the clock signal.
11. The memory apparatus as claimed in claim 8 , wherein, when the temperature measured by a temperature sensor associated with a memory device is below a lower limiting value for the operating temperature, less than one word line per memory bank is addressed on average, upon each pulse of the clock signal, wherein, the word lines are counted in a manner encompassing the memory banks and, wherein, after a last word line of a memory bank has been addressed, a first word line of another memory bank of the same memory device is addressed in the next pulse of the clock signal.
12. The memory apparatus as claimed in claim 1 , wherein each memory bank respectively has a plurality of memory segments, a group of word lines arranged in each memory segment, wherein the memory cells of a respective memory segment are connected to the group of word lines.
13. The memory apparatus as claimed in claim 12 , wherein the sub-units of the memory banks are either respective memory segments or respectively comprise a plurality of memory segments.
14. The memory apparatus as claimed in claim 12 , wherein the word lines comprise segmented word lines that each have a plurality of word line segments, and wherein each sub-unit of a memory bank respectively comprises precisely one word line segment of each word line of the respective memory bank.
15. The memory apparatus as claimed in claim 1 , wherein a first operating mode or a second operating mode of the memory apparatus can be selectively set, wherein the number of memory cells simultaneously refreshed per pulse of the clock signal in the first operating mode is temperature-dependent, and wherein the number of memory cells simultaneously refreshed per pulse of the clock signal in the second operating mode is dependent on the local temperature measured by the temperature sensor assigned to the respective memory device.
16. The memory apparatus as claimed in claim 1 , wherein the electronic memory apparatus comprises a memory module.
17. An electronic memory apparatus comprising: a plurality of memory devices each having a plurality of nonvolatile memory cells that are refreshed during operation of the electronic memory apparatus; a control unit coupled to the plurality of memory devices to pass a same periodic clock signal to each of the memory devices, the clock signal causing the memory cells to be refreshed in the memory devices; and a plurality of temperature sensors, each temperature sensor associated with a respective memory device to measure a local temperature near the respective memory device during operation; wherein the memory devices are memory modules that each have a plurality of integrated memory chips, wherein the memory cells are connected to word lines, wherein based on the measured local temperature, and without changing the frequency of the clock signal, each memory device individually determines a refresh time by changing the number of memory cells simultaneously refreshed, and wherein the number of memory cells simultaneously refreshed is changed by changing the number of word lines simultaneously addressed in each pulse of the clock signal.
18. The memory apparatus as claimed in claim 17 , wherein each memory module forwards the clock signal to all of the integrated memory chips of that memory module.
19. The memory apparatus as claimed in claim 17 , wherein the memory modules use the periodic clock signal to count and address the word lines of the memory chips of the respective memory module, wherein the memory cells connected to addressed word lines respectively are refreshed, and wherein, word lines other than those in the respective preceding pulse of the clock signal are addressed in each pulse of the clock signal.
20. The memory apparatus as claimed in claim 17 , wherein, when the temperature measured by a temperature sensor associated with a respective memory module is within a prescribed bandwidth for an operating temperature, precisely one word line is addressed in all of the memory chips of the respective memory module upon each pulse of the clock signal, wherein, the word lines of the respective memory chips are counted from a first word line to a last word line of the respective memory chip, wherein, after the last word line of the respective memory chip has been addressed, the first word line of the respective memory chip is addressed again in the next pulse of the clock signal.
21. The memory apparatus as claimed in claim 17 , wherein, when the temperature measured by a temperature sensor associated with a respective memory module is above an upper limiting value for the operating temperature, 2n word lines are respectively addressed in each memory chip of the respective memory module upon each pulse of the clock signal, wherein, n is a natural number, and wherein the word lines are counted from a first word line to a last word line in partial regions of the memory chips, and wherein, after the last word line of the respective partial region of the memory chip has been addressed, the first word line of the respective partial region of the memory chip is addressed again in the next pulse of the clock signal.
22. The memory apparatus as claimed in claim 17 , wherein, when the temperature measured by a temperature sensor associated with a respective memory module is below a lower limiting value for the operating temperature, less than one word line per memory chip is addressed on average, in each pulse of the clock signal, wherein the word lines are counted in a manner encompassing the memory chips, and wherein, after a last word line of a memory chip has been addressed, a first word line of another memory chip of the respective memory module is addressed in the next pulse of the clock signal.
23. An electronic memory apparatus comprising: memory devices, wherein each memory device comprises memory cells, wherein the memory cells are refreshed during operation of the electronic memory apparatus; a control unit coupled to the memory devices to pass a same periodic clock signal to each of the memory devices, the clock signal refreshing the memory cells in the memory devices; and temperature sensors, wherein each memory device comprises a temperature sensor to measure a local temperature during operation; wherein each memory device individually determines a refresh time by changing the number of memory cells simultaneously refreshed based on the local temperature in the memory device and without changing the frequency of the clock signal, wherein, if the local temperature exceeds an upper limiting temperature the number of memory cells simultaneously refreshed is increased by increasing the number of word lines simultaneously addressed in each pulse of the clock signal.
24. The memory apparatus of claim 23 , wherein, if the local temperature is less than a lower limiting temperature, the number of memory cells simultaneously refreshed is decreased by decreasing the number of word lines simultaneously addressed in each pulse of the clock signal.
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June 1, 2006
July 22, 2008
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