An array of grooves (23) is formed in a first side (12) of a wafer (10) during a wafer processing method. A back grinding tape (16) is adhered to the first side. An amount of material is removed from the second side (20) of the wafer. An adhesive layer (30) is applied to the second side. Dicing tape (24) is applied to the adhesive layer to create a first wafer assembly (32). The first wafer assembly is supported on a support surface (34) with the dicing tape facing the support surface and the back grinding tape exposed. The back grinding tape is removed and the adhesive layer is severed through the array of grooves to create individually removable die (28).
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor wafer processing system, comprising: a first wafer processing station for (a) forming an array of grooves in a first side of a semiconductor wafer to a chosen depth which is 70-90 percent of a chosen thickness of the semiconductor wafer, (b) applying a back-grinding tape to the first side of the semiconductor wafer, (c) back-grinding a second side of the semiconductor wafer until the semiconductor wafer has the chosen thickness, wherein the back-grinding removes a portion of the second side of the semiconductor wafer without exposing the grooves from the second side of the semiconductor wafer which leaves a remaining portion across the second side of the semiconductor wafer, (d) applying an adhesive layer to the remaining portion of the second side of the semiconductor wafer, and (e) applying a first side of dicing tape over the adhesive layer; and a second wafer processing station having a vacuum table for securing a second side of the dicing tape, the second wafer processing station including, (f) means for removing tho back-grinding tape, and (g) means for severing the remaining portion of the second side of the semiconductor wafer, adhesive layer, and dicing tape to provide individually removable die from the semiconductor wafer without having incurred die tilt from the first and second wafer processing station features (a) - (g).
2. The semiconductor wafer processing system of claim 1 , wherein the adhesive layer has a thickness of 20-75 micrometers.
3. The semiconductor wafer processing system of claim 1 , wherein the adhesive layer includes a film adhesive.
4. The semiconductor wafer processing system of claim 1 , wherein the means for severing includes a grinding wheel.
5. The semiconductor wafer processing system of claim 1 , wherein the adhesive layer and dicing tape are applied simultaneously.
6. A semiconductor wafer processing system, comprising: a first wafer processing station for (a) forming an array of grooves in a first side of a semiconductor wafer to a chosen depth which is about 20 percent greater than a chosen thickness of the semiconductor wafer, (b) applying a back-grinding tape to the first side of the semiconductor wafer, (c) back-grinding a second side of the semiconductor wafer until the semiconductor wafer has the chosen thickness, wherein the back-grinding exposes the grooves from the second side of the semiconductor wafer, (d) applying an adhesive layer to the second side of the semiconductor wafer, and (e) applying a first side of dicing tape over the adhesive layer; and a second wafer processing station having a vacuum table for securing a second side of the dicing tape, the second wafer processing station including, (f) means for removing the back-grinding tape, and (g) means for severing the adhesive layer and dicing tape to provide individually removable die from the semiconductor wafer without having incurred die tilt from the first and, second wafer processing station features (a) - (g).
7. The semiconductor wafer processing system of claim 6 , wherein the adhesive layer has a thickness of 20-75 micrometers.
8. The semiconductor wafer processing system of claim 6 , wherein the adhesive layer includes a film adhesive.
9. The semiconductor wafer processing system of claim 6 , wherein the means for severing includes a grinding wheel.
10. The semiconductor wafer processing system of claim 6 , wherein the adhesive layer and dicing tape are applied simultaneously.
11. A semiconductor wafer processing system, comprising: a first wafer processing station for (a) forming an array of grooves in a first side of a semiconductor wafer to a chosen depth, (b) applying a back-grinding tape to the first side of the semiconductor wafer, (c) back-grinding a second side of the semiconductor water until the semiconductor wafer has a chosen thickness, (d) applying an adhesive layer to the second side of the semiconductor wafer, and (e) applying a first side of dicing tape over the adhesive layer; and a second wafer processing station having a support table for securing a second side of the dicing tape, the second wafer processing station including, (f) means for removing the back-grinding tape, and (g) means for severing the adhesive layer and dicing tape to provide individually removable die from the semiconductor wafer without having incurred die tilt from the first and second wafer processing station features (a) - (g).
12. The semiconductor wafer processing system of claim 11 , wherein the chosen depth of the grooves is 70-90 percent of the chosen thickness of the semiconductor wafer.
13. The semiconductor wafer processing system of claim 11 , wherein the chosen depth of the grooves is 20 percent greater than the chosen thickness of the semiconductor wafer.
14. The semiconductor wafer processing system of claim 11 , wherein the adhesive layer has a thickness of 20-75 micrometers.
15. The semiconductor wafer processing system of claim 11 , wherein the adhesive layer includes a film adhesive.
16. The semiconductor wafer processing system of claim 11 , wherein the first wafer processing station includes a grinding wheel.
17. The semiconductor water processing system of claim 11 , wherein the means for severing includes a grinding wheel.
18. The semiconductor wafer processing system of claim 11 , wherein the means for severing occurs through the grooves.
19. The semiconductor wafer processing system of claim 11 , wherein the adhesive layer and dicing tape are applied simultaneously.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 13, 2006
September 2, 2008
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