A hysteretic regulator is provided. The hysteretic regulator includes a delay compensation circuit that adds a delay to the output of the hysteretic comparator. The delay is dependent on the input voltage. For low duty cycles, the slope of the inductor current is much greater for the rising edge than it is for the falling edge. The delay compensation circuit adds sufficient delay to the falling edge so that the undershoot cancels the overshoot.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A circuit for regulation, comprising: a regulator controller that is operable to control conversion of an input voltage to a regulated output voltage, wherein the regulator controller includes: a comparator that is operable to provide a comparator output signal that is based, in part, on at least one of an inductor current or the regulated output voltage; and a delay compensation circuit that is operable to provide a driver input signal from the comparator output signal by adding a compensation delay to the comparator output signal such that the compensation delay is sufficient to approximately correct an error in the regulated output voltage, wherein the regulated output voltage is based, in part, on the driver input signal.
2. The circuit of claim 1 , wherein the compensation delay is sufficient to approximately correct for overshoot error in the regulated output voltage caused by a duty cycle of the comparator output signal being greater than 50%.
3. The circuit of claim 1 , wherein the compensation delay is sufficient to approximately correct for undershoot error in the regulated output voltage caused by a duty cycle of the comparator output signal being less than 50%.
4. The circuit of claim 1 , wherein the compensation delay is sufficient to approximately correct for overshoot error caused by reduced inductance of an inductor occurring with increased inductor current.
5. The circuit of claim 1 , wherein the circuit for regulation has one of a buck, boost, or buck/boost topology.
6. The circuit of claim 1 , further comprising: a switch circuit that is coupled between the input voltage and a switch node, wherein the switch circuit has a control input; a driving having: an input that is coupled to the driver input signal, and an output that is coupled to the control input of the switch circuit; and an inductor that is coupled between the switch node and the regulated output voltage, wherein the inductor is operable to provide the inductor current.
7. The circuit of claim 1 , wherein the regulator controller is a constant-on-time regulator controller.
8. The circuit of claim 1 , wherein the regulator controller is a hysteretic regulator controller; the comparator is a hysteretic comparator; the hysteretic comparator includes a first input and a second input; the hysteretic comparator is arranged to receive a first comparator input voltage (V 1 ) at the first input of the hysteretic comparator; the hysteretic comparator is arranged to receive a second comparator voltage (V 2 ) at the second input of the hysteretic comparator; and wherein the hysteretic comparator is operable to assert the comparator output signal if the first voltage V 1 reaches V2+Vhys after a time delay td), where Vhys represents a hysteresis voltage that is associated with the hysteretic comparator; and wherein the hysteretic comparator is operable to unassert the comparator output signal if the first voltage V 1 reaches V2+Vhys after approximately the time delay td.
9. The circuit of claim 8 , wherein the regulator controller does not include an error amplifier.
10. The circuit of claim 8 , further comprising: a voltage divider, including a first resistor that is coupled between the regulated output voltage and a node, and a second resistor that is coupled between the node and ground, wherein the first voltage is provided at the node; and a reference voltage circuit that is arranged to provide the second voltage.
11. The circuit of claim 8 , further comprising: a sense resistor that is coupled between the output voltage and the first input of the hysteretic comparator; a reference voltage circuit having at least an output; a first resistor that is coupled between the output voltage and the second input of the hysteretic comparator; and a second resistor that is coupled between the second input of the hysteretic comparator and the output of the reference voltage circuit.
12. The circuit of claim 8 , wherein the compensation delay is approximately td*(VIN−2VO)/VO, where VIN represents the input voltage and VO represents the regulated output voltage.
13. A circuit for regulation, comprising: a hysteretic power regulator controller that is operable to control hysteretic conversion of an input voltage to a regulated output voltage, wherein the hysteretic power regulator controller includes: a hysteretic comparator that is operable to provide a hysteretic comparator output signal that is based, in part, on at least one of an inductor current or the regulated output voltage; and a delay compensation circuit that is operable to provide a driver input signal from the hysteretic comparator output signal by adding an input-voltage-dependent delay to the hysteretic comparator output signal such that the input-voltage-dependent delay is sufficient to approximately correct overshoot error in the regulated output voltage, wherein the regulated output voltage is based, in part, on the driver input signal.
14. The circuit of claim 13 , wherein the hysteretic power regulator controller does not include an error amplifier, and does not include a compensation network.
15. A method for error correction, comprising: converting an input signal into a regulated output signal, wherein converting the input signal into the regulated output signal includes: performing a comparison to provide a comparison output signal, wherein the comparison is based, in part, on at least one of an inductor current and the regulated output signal; providing a delay compensation output signal by adding a compensation delay to the comparator output signal such that the compensation delay is sufficient to approximately correct an error in the regulated output voltage; and driving a switch based, at least in part, on the delay compensation output signal.
16. The method of claim 15 , wherein performing the comparison includes comparing a current command voltage with a current sense voltage, wherein the current sense voltage is based, in part, on the inductor current.
17. The method of claim 15 , wherein performing the comparison includes comparing a feedback voltage with a reference voltage; wherein the feedback voltage is based, in part, on the regulated output voltage.
18. The method of claim 15 , further comprising: employing an inductor to provide the inductor current, wherein providing the delay compensation output signal includes: determining whether the inductor current reaches a current limit that corresponds to a current value at which the inductance of the inductor changes to a free-air value; and if the inductor current reaches the current limit, adding sufficient compensation delay that the regulated output voltage is substantially unchanged when the inductance changes to the free-air value.
19. The method of claim 15 , wherein: performing the comparison includes: comparing a first voltage with a second voltage; asserting the comparison output signal if the first voltage reaches the second voltage plus a hysteresis voltage after a delay time (td); and unasserting the comparison output signal if the first voltages reaches the second voltage minus a hysteresis voltage after about the delay time (td).
20. The method of claim 19 , wherein providing the delay compensation output signal includes: adding a delay of about td*(VIN−2VO)/VO to the falling edge of the comparator output signal to provide the delay compensation output signal, wherein VIN represent the input voltage and VO represents the regulated output voltage.
21. The circuit of claim 1 , wherein the delay compensation circuit is operable to provide the driver input signal from the comparator output signal by adding the compensation delay to the comparator output signal whenever the comparator is operating.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 4, 2005
September 9, 2008
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