Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of phase change material patterns are two-dimensionally arrayed on the insulating layer, and the phase change material patterns are electrically connected to the second semiconductor patterns, respectively.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of fabricating a phase change memory device, comprising: forming a plurality of parallel word lines and a word line isolation layer filling a gap region between the word lines on a semiconductor substrate of a first conductivity type, the word lines being formed to have a second conductivity type different from the first conductivity type; forming an upper molding layer on the word lines and the word line isolation layer; patterning the upper molding layer to form a plurality of upper openings exposing predetermined regions of the word lines; sequentially forming first semiconductor patterns and second semiconductor patterns in the upper openings, the first semiconductor patterns being formed to have the first conductivity type or the second conductivity type, and the second semiconductor patterns being formed to have the first conductivity type; and forming a plurality of phase change material patterns over the second semiconductor patterns respectively, the phase change material patterns being each electrically connected to the second semiconductor patterns.
2. The method according to claim 1 , wherein forming the word lines and the word line isolation layer comprising: providing a semiconductor substrate of a first conductivity type; forming an upper epitaxial layer having a second conductivity type different from the first conductivity type on the semiconductor substrate; patterning the upper epitaxial semiconductor layer to form a plurality of parallel upper epitaxial semiconductor patterns; forming an insulating layer on the substrate having the upper epitaxial semiconductor patterns; and planarizing the insulating layer to expose top surfaces of the upper epitaxial semiconductor patterns.
3. The method according to claim 1 further comprises forming buffer lines under the word lines.
4. The method according to claim 3 , wherein forming the buffer lines, the word lines and the word line isolation layer comprising: providing a semiconductor substrate of a first conductivity type; sequentially forming a lower epitaxial semiconductor layer having the first conductivity type and an upper epitaxial semiconductor layer having a second conductivity type different from the first conductivity type on the semiconductor substrate; patterning the upper epitaxial semiconductor layer and the lower epitaxial semiconductor layer to form lower epitaxial semiconductor patterns and upper epitaxial semiconductor patterns, which are sequentially stacked; forming an insulating layer on the substrate having the upper epitaxial semiconductor patterns; and planarizing the insulating layer to expose top surfaces of the upper epitaxial semiconductor patterns.
5. The method according to claim 1 , wherein forming the word lines and the word line isolation layer comprising: forming a lower molding layer on a semiconductor substrate of a first conductivity type; patterning the lower molding layer to form a plurality of parallel lower openings exposing predetermined regions of the semiconductor substrate; and forming a plurality of semiconductor lines in the lower openings using a selective epitaxial growth technique or a solid phase epitaxial technique, wherein the semiconductor lines are formed to have a second conductivity type different from the first conductivity type.
6. The method according to claim 5 , further comprises forming a plurality of buffer lines in lower regions of the lower openings using a selective epitaxial growth technique or a solid phase epitaxial technique prior to formation of the semiconductor lines, wherein the buffer lines are formed to have the first conductivity type.
7. The method according to claim 1 , wherein forming the word lines and the word line isolation layer comprising: forming a trench isolation layer in a predetermined region of a semiconductor substrate having a first conductivity type to define a plurality of parallel active regions; and implanting impurity ions having a second conductivity type different from the first conductivity type into the active regions to form word lines of the second conductivity type.
8. The method according to claim 7 further comprises implanting impurity ions of the first conductivity type into the active regions to form buffer lines of the first conductivity type under the word lines, before of after formation of the word lines.
9. The method according to claim 1 , wherein the first and second semiconductor patterns are formed using a selective epitaxial growth technique or a solid phase epitaxial technique.
10. The method according to claim 1 further comprises forming a plurality of conductive plugs on the second semiconductor patterns respectively, wherein the conductive plugs as well as the first and second semiconductor patterns are formed in the upper openings.
11. The method according to claim 1 , wherein the first conductivity type is a P-type, and the second conductivity type is an N-type.
12. The method according to claim 1 , wherein the semiconductor substrate is a single crystal semiconductor substrate, and the word lines, the first semiconductor patterns and the second semiconductor patterns are single crystal semiconductor patterns.
13. The method according to claim 1 , wherein the first semiconductor patterns are formed to have an impurity concentration lower than those of the second semiconductor patterns and the word lines.
14. The method according to claim 1 , further comprising: forming an interlayer insulating layer on the substrate having the phase change material patterns; pattering the interlayer insulating layer to form bit line contact holes exposing the phase change material patterns; and forming a plurality of bit lines covering the bit line contact holes on the interlayer insulating layer, wherein the bit lines are formed to cross over the word lines.
15. A method of fabricating a phase change memory device, comprising: forming a first molding layer on a semiconductor substrate of a first conductivity type; patterning the first molding layer to form first openings exposing predetermined regions of the semiconductor substrate; forming a plurality of word lines in lower regions of the first openings, the word lines being formed to have a second conductivity type different from the first conductivity type; forming second molding layer patterns filling upper regions of the first openings, the second molding layer patterns being formed of an insulating layer having an etch selectivity with respect to the first molding layer; patterning the second molding layer patterns to form separating walls which provide a plurality of second openings that expose predetermined regions of the word lines; sequentially forming first semiconductor patterns and second semiconductor patterns in the second openings, the first semiconductor patterns being formed to have the first conductivity type or the second conductivity type and the second semiconductor patterns being formed to have the first conductivity type; and forming a plurality of phase change material patterns over the second semiconductor patterns, the phase change material patterns being electrically connected to the second semiconductor patterns respectively.
16. The method according to claim 15 , wherein the first conductivity type is a P-type, and the second conductivity type is an N-type.
17. The method according to claim 15 , wherein the first molding layer is formed of a silicon oxide layer, and the second molding layer patterns are formed of a silicon nitride layer.
18. The method according to claim 15 , wherein the word lines are formed using a selective epitaxial growth technique or a solid phase epitaxial technique.
19. The method according to claim 15 further comprises forming buffer lines on the semiconductor substrate exposed by the first openings using a selective epitaxial growth technique or a solid phase epitaxial technique prior to formation of the word lines, wherein the buffer lines are formed to have the first conductivity type.
20. The method according to claim 15 , wherein forming the second molding layer patterns comprising: forming a second molding layer having an etch selectivity with respect to the first molding layer on the substrate having the word lines; and planarizing the second molding layer to expose top surfaces of the first molding layer.
21. The method according to claim 20 , wherein the first molding layer is formed of a silicon oxide layer, and the second molding layer is formed of a silicon nitride layer.
22. The method according to claim 15 , wherein forming the separating walls comprising: forming a photoresist pattern on the substrate having the second molding layer patterns, the photoresist pattern being formed to have a plurality of openings crossing over the word lines; and etching the second molding layer patterns using the photoresist pattern as an etching mask to form a plurality of second openings that expose predetermined regions of the word lines.
23. The method according to claim 15 , wherein the first semiconductor patterns are formed to have an impurity concentration lower than those of the second semiconductor patterns and the word lines.
24. The method according to claim 15 , wherein the first and second semiconductor patterns are formed using a selective epitaxial growth technique or a solid phase epitaxial technique.
25. The method according to claim 15 further comprises forming a plurality of conductive plugs on the second semiconductor patterns respectively, wherein the conductive plugs as well as the first and second semiconductor patterns are formed in the second openings.
26. The method according to claim 25 , wherein forming the conductive plugs comprising: forming a metal layer on the substrate having the second semiconductor patterns; and planarizing the metal layer to expose a surface of the first molding layer and surfaces of the separating walls.
27. The method according to claim 26 further comprises selectively forming a metal silicide layer on surfaces of the second semiconductor patterns prior to formation of the metal layer.
28. The method according to claim 15 , wherein the first openings are formed to have line-shaped configurations, which are parallel to each other.
29. The method according to claim 15 , wherein the semiconductor substrate is a single crystal semiconductor substrate, and the word lines, the first semiconductor patterns and the second semiconductor patterns are single crystal semiconductor patterns.
30. The method according to claim 15 , further comprising: forming an interlayer insulating layer on the substrate having the phase change material patterns; pattering the interlayer insulating layer to form bit line contact holes exposing the phase change material patterns; and forming a plurality of bit lines covering the bit line contact holes on the interlayer insulating layer, wherein the bit lines are formed to cross over the word lines.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 30, 2005
September 23, 2008
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