An integrated circuit (IC) includes a strained-silicon layer formed by deposition of amorphous silicon onto either a region of a semiconductor layer that has been implanted with ions to create a larger spacing between atoms in a crystalline lattice of the semiconductor layer or a silicon-ion layer that has been epitaxially grown on the semiconductor layer to have an increased spacing between atoms in the silicon-ion layer. Alternatively, the IC includes a strained-silicon layer formed by silicon epitaxial growth onto the region of the semiconductor layer that has been implanted with ions. The IC also preferably includes a CMOS device that preferably, but not necessarily, incorporates sub-0.1 micron technology. The implanted ions may preferably be heavy ions, such as germanium ions, antimony ions or others. Ion implantation may be done with a single implantation process, as well as with multiple implantation processes.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming a portion of an integrated circuit comprising: providing a semiconductor layer; implanting heavy ions into at least a portion of the semiconductor layer not previously containing the heavy ions; recrystallizing the ion-implanted portion of the semiconductor layer; depositing amorphous silicon onto the ion-implanted portion of the semiconductor layer; and forming a strained-silicon layer in the deposited amorphous silicon, the strain being induced by the recrystallized ion-implanted portion of the semiconductor layer.
2. A method as defined in claim 1 further comprising: forming a CMOS device on the strained-silicon layer, the CMOS device having a channel region formed in the strained-silicon layer.
3. A method of forming an integrated circuit comprising: providing a semiconductor layer; forming a region of the semiconductor layer having desired ions therein by implanting the desired ions into the region of the semiconductor layer; depositing an amorphous silicon layer on the region of the semiconductor substrate having the desired ions therein; forming a CMOS device above the amorphous silicon layer.
4. A method as defined in claim 3 further comprising: providing the semiconductor layer having a crystalline lattice; and the step of forming the region of the semiconductor layer having the desired ions therein further comprising: forming the desired ions in substitutional positions in the crystalline lattice of the semiconductor layer by implanting the desired ions into the region of the semiconductor layer and recrystallizing the region of the semiconductor layer by annealing the crystalline lattice.
5. A method as defined in claim 4 further comprising: generating a larger spacing between atoms of the crystalline lattice of the region of the semiconductor layer having the desired ions therein by the step of forming the desired ions in substitutional positions in the crystalline lattice.
6. A method as defined in claim 5 further comprising: upon depositing the amorphous silicon layer, converting the amorphous silicon layer into a strained-silicon layer.
7. A method as defined in claim 3 further comprising: forming a graded ion concentration in the region of the semiconductor layer having desired ions therein by implanting the desired ions using a single ion implantation step.
8. A method as defined in claim 3 further comprising: forming a graded ion concentration in the region of the semiconductor layer having desired ions therein by implanting the desired ions using multiple ion implantations.
9. A method as defined in claim 3 further comprising: depositing the amorphous silicon layer to a thickness of about 50-300 Angstroms.
10. A method as defined in claim 3 wherein: the step of forming the region of the semiconductor layer having the desired ions therein further comprises: implanting heavy ions into the region of the semiconductor layer.
11. A method as defined in claim 10 wherein: the step of implanting the heavy ions further comprises: implanting germanium ions into the region of the semiconductor layer.
12. A method as defined in claim 10 wherein: the step of implanting the heavy ions further comprises: implanting antimony ions into the region of the semiconductor layer.
13. A method of forming a portion of an integrated circuit comprising: providing a semiconductor layer; epitaxially growing a silicon-ion layer onto the portion of the semiconductor layer; depositing amorphous silicon onto the silicon-ion layer; and forming a strained-silicon layer in the deposited amorphous silicon, the strain being induced by the epitaxially grown silicon-ion layer.
14. An integrated circuit comprising: a semiconductor layer; a layer of one of: (a) an ion-implanted region formed in the semiconductor layer, and (b) an epitaxially grown silicon-ion formed on the semiconductor layer; a strained-silicon layer formed by one of: (c) amorphous silicon deposition on the ion-implanted region of the semiconductor layer, and (d) amorphous silicon deposition on the epitaxially grown silicon-ion layer; and a CMOS device formed on the strained-silicon layer.
15. An integrated circuit as defined in claim 14 wherein the strained-silicon layer is formed to a thickness of about 50-300 Angstroms.
16. An integrated circuit as defined in claim 14 wherein: the semiconductor layer has a crystalline lattice; and for the ion-implanted region of the semiconductor layer desired ions increase spacing between atoms of the crystalline lattice.
17. An integrated circuit as defined in claim 14 wherein: for the ion-implanted region: a graded ion concentration of desired ions is formed in the ion-implanted region by implanting the desired ions into the semiconductor layer using a single ion implantation step.
18. An integrated circuit as defined in claim 14 wherein: for the ion-implanted region: a graded ion concentration of desired ions is formed in the ion-implanted region by implanting the desired ions into the semiconductor layer using multiple ion implantations.
19. An integrated circuit as defined in claim 14 wherein the ion-implanted region and the epitaxially grown silicon-ion layer include heavy ions therein.
20. An integrated circuit as defined in claim 19 wherein the heavy ions include germanium ions.
21. An integrated circuit as defined in claim 19 wherein the heavy ions include antimony ions.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 4, 2003
September 30, 2008
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