A method of fabricating and a structure of an IC incorporating strained MOSFETs on separated silicon layers are disclosed. N-channel field effect transistors (nFET) and P-channel FETs (pFET) are formed on the separated silicon layers, respectively. Shallow trench insulation (STI) regions adjacent to the nFETs and pFETs thus can be formed to induce different stress to the channel regions of the respective nFETs and pFETs. As a consequence, performance of both the nFETs and the pFETs can be improved by the STI stress. In addition, the area of the IC can also be reduced as the two silicon layers are positioned vertically relative to one another.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit (IC) comprising: two silicon layers separated by a dielectric layer, one of the two silicon layers located above the other one; an N-channel field effect transistor (nFET) formed on one of the two silicon layers, and a P-channel field effect transistor (pFET) formed on the other one of the two silicon layers; and a first shallow trench isolation (STI) adjacent to the nFET, and a second STI adjacent to the pFET, wherein the first STI and the second STI induce different stress in a channel region of the nFET and a channel region of the pFET, respectively.
2. The integrated circuit of claim 1 , wherein the first STI induces tensile stress and the second STI induces compressive stress.
3. The integrated circuit of claim 1 , further comprising a first liner layer on the nFET and a second liner layer on the pFET, wherein the first liner layer and the second liner induce different stress in the channel region of the nFET and the channel region of the pFET, respectively.
4. The integrated circuit of claim 3 , wherein the first liner layer induces tensile stress and the second liner layer induces compressive stress.
5. The integrated circuit of claim 1 , wherein a silicide of the nFET and a silicide of the pFET include different silicide stress.
6. The integrated circuit of claim 1 , wherein the first and the second silicon layers are of different crystalline orientations.
7. The integrated circuit of claim 1 , wherein a contact to a device on a lower one of the silicon layers extends through an upper one of the silicon layers and is insulated from silicon of the upper one of the silicon layers.
8. The integrated circuit of claim 7 , wherein the contact extends through a STI on the upper one of the silicon layers.
9. An integrated circuit (IC) comprising: an N-channel field effect transistor (nFET) on a first silicon layer; a first shallow trench insulation (STI) adjacent to the nFET on the first silicon layer, the first STI inducing tensile stress on a channel region of the nFET; a P-channel FET (pFET) on a second silicon layer; and a second STI adjacent to the pFET on the second silicon layer, the second STI inducing compressive stress on a channel region of the pFET; wherein the first silicon layer and the second silicon layer are positioned differently vertically relative to one another.
10. The integrated circuit of claim 9 , further comprising a tensile liner layer covering the nFET.
11. The integrated circuit of claim 9 , further comprising a compressive liner layer covering the pFET.
12. The integrated circuit of claim 9 , wherein a silicide of the nFET and a silicide of the pFET include different silicide stress.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 10, 2006
October 14, 2008
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