According to one embodiment, a method of test error detection for a wafer having a plurality of rows of integrated circuit (IC) chips is provided. The method includes determining that a first number of IC chips that are indicated as failing a test has increased from a first row to a second row immediately following the first row at least by a first threshold. The method also includes determining that a second number of IC chips that are indicated as failing the test has decreased from a previous row to a second row immediately following the previous row at least by a second threshold. The method also includes indicating that a group of one or more rows located between the first row and the second row includes one or more IC chips that have been tested incorrectly.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of test error detection for a wafer having a plurality of rows of integrated circuit (IC) chips, comprising: determining that a first number of IC chips that are indicated as failing a test has increased by at least a first threshold from a first row to a row following the first row; determining that a second number of IC chips that are indicated as failing the test has decreased by at least a second threshold from a row previous to a second row, wherein the second row follows the first row; and determining that a group of one or more rows located between the first row and the second row includes one or more IC chips that have been tested incorrectly.
2. The method of claim 1 , wherein the first threshold and the second threshold each equals 10.
3. The method of claim 1 , wherein the first threshold and the second threshold each equals approximately five percent of a total number of IC chips in a row.
4. The method of claim 1 , wherein the first threshold and the second threshold are different values.
5. The method of claim 1 , wherein determining that a group of one or more rows includes one or more IC chips that have been tested incorrectly comprises determining that a first total number of IC chips in the group of rows is less than a threshold value, wherein the threshold value comprises a percentage value of a second total number of IC chips in all of the rows of the wafer.
6. The method of claim 5 , wherein the percentage value is approximately 25 percent.
7. The method of claim 1 , wherein determining that a group of one or more rows includes one or more IC chips that have been tested incorrectly comprises determining whether a number of rows in the group of rows is less than a third threshold.
8. The method of claim 7 , wherein the third threshold is equal to 6.
9. The method of claim 1 , wherein determining that a group of one or more rows includes one or more IC chips that have been tested incorrectly comprises determining that the first row and the second row each comprises at least one IC chip indicated as passing the test.
10. The method of claim 1 , wherein the row following the first row immediately follows the first row.
11. The method of claim 1 , wherein the second row immediately follows the row previous to the second row.
12. The method of claim 1 , wherein the row following the first row and the row previous to the second row comprise the same row.
13. A system of test error detection, comprising: a platform operable to support a wafer having a plurality of rows of integrated circuit (IC) chips; a probe system operable to probe each IC chip; a testing device coupled to the probe system and operable to test each IC chip through the probe system; and a computer system operable to: determine that a first number of IC chips that are indicated as failing a test has increased by at least a first threshold from a first row to a row following the first row; determine that a second number of IC chips that are indicated as failing the test has decreased by at least a second threshold from a row previous to a second row, wherein the second row follows the first row; and determine that a group of one or more rows located between the first row and the second row includes one or more IC chips that have been tested incorrectly.
14. The system of claim 13 , wherein the first threshold and the second threshold each equals 10.
15. The system of claim 13 , wherein the first threshold and the second threshold each equals approximately five percent of a total number of IC chips in a row.
16. The system of claim 13 , wherein the first threshold and the second threshold are different values.
17. The system of claim 13 , wherein the computer system is operable to determine that a group of one or more rows includes one or more IC chips that have been tested incorrectly by determining that a first total number of IC chips in the group of rows is less than a threshold value, wherein the threshold value comprises a percentage value of a second total number of IC chips in all of the rows of the wafer.
18. The system of claim 17 , wherein the percentage value is approximately 25 percent.
19. The system of claim 13 , wherein the computer system is operable to determine that a group of one or more rows includes one or more IC chips that have been tested incorrectly by determining whether a number of rows in the group of rows is less than a third threshold.
20. The system of claim 19 , wherein the third threshold is equal to 6.
21. The system of claim 13 , wherein the computer system is operable to determine that a group of one or more rows includes one or more IC chips that have been tested incorrectly by determining that the first row and the second row each comprises at least one IC chip indicated as passing the test.
22. The system of claim 13 , wherein the row following the first row immediately follows the first row.
23. The system of claim 13 , wherein the second row immediately follows the row previous to the second row.
24. The system of claim 13 , wherein the row following the first row and the row previous to the second row comprise the same row.
25. An apparatus for detecting an error of a test conducted on a wafer having a plurality of rows of integrated circuit (IC) chips, the apparatus comprising: a computer-readable medium; and a program stored in the computer-readable medium, the program, when executed using a processor of a computer, operable to: determine that a first number of IC chips that are indicated as failing a test has increased by at least a first threshold from a first row to a row following the first row; determine that a second number of IC chips that are indicated as failing the test has decreased by at least a second threshold from a row previous to a second row, wherein the second row follows the first row; and determine that a group of one or more rows located between the first row and the second row includes one or more IC chips that have been tested incorrectly.
26. The apparatus of claim 25 , wherein the first threshold and the second threshold each equals 10.
27. The apparatus of claim 25 , wherein the first threshold and the second threshold each equals approximately five percent of a total number of IC chips in a row.
28. The apparatus of claim 25 , wherein the first threshold and the second threshold are different values.
29. The apparatus of claim 25 , wherein the program is operable to determine that a group of one or more rows includes one or more IC chips that have been tested incorrectly by determining that a first total number of IC chips in the group of rows is less than a threshold value, wherein the threshold value comprises a percentage value of a second total number of IC chips in all of the rows of the wafer.
30. The apparatus of claim 29 , wherein the percentage value is approximately 25 percent.
31. The apparatus of claim 25 , wherein the program is operable to determine that a group of one or more rows includes one or more IC chips that have been tested incorrectly by determining whether a number of rows in the group of rows is less than a third threshold.
32. The apparatus of claim 31 , wherein the third threshold is equal to 6.
33. The apparatus of claim 25 , wherein the program is operable to determine that a group of one or more rows includes one or more IC chips that have been tested incorrectly by determining that the first row and the second row each comprises at least one IC chip indicated as passing the test.
34. The apparatus of claim 25 , wherein the row following the first row immediately follows the first row.
35. The apparatus of claim 25 , wherein the second row immediately follows the row previous to the second row.
36. The apparatus of claim 25 , wherein the row following the first row and the row previous to the second row comprise the same row.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 16, 2004
October 14, 2008
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