A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory device, comprising: a p-doped substrate; a plurality of electrically-conductive bit lines extending along a bit line direction; a plurality of electrically-conductive word lines extending along a word line direction; a plurality of electrically-conductive control gate lines extending along said word line direction; and a plurality of memory cells arranged respectively along said bit lines and said word lines, wherein each memory cell comprises: a program/erase PMOS transistor including a first gate, and first and second P+ regions formed within an n-doped well which, in turn, is formed within said p-doped substrate, wherein said first P+ region is electrically connected to a corresponding bit line; an access PMOS transistor including a second gate, and third and fourth P+ regions formed within said n-doped well, wherein said third P+ region is electrically connected to said second P+ region of said program/erase PMOS transistor, and said second gate is electrically connected to a corresponding word line; and a control gate NMOS transistor formed in a p-doped pocket which, in turn, is formed within said n-doped well, wherein said control gate NMOS transistor comprises a third gate, and first and second N+ regions formed within said p-doped pocket, wherein said first and second N+ regions are electrically connected to a corresponding control gate line, and said third gate is electrically connected to said first gate of said program/erase PMOS transistor to form a floating gate.
2. The memory device of claim 1 , wherein said first and second N+ regions are electrically connected to said corresponding control gate line by way of an electrically-conductive layer formed above said p-doped substrate.
3. The memory device of claim 1 , further comprising a fifth P+ region formed within said p-doped pocket, wherein said fifth P+ region is electrically connected to said corresponding control gate line.
4. The memory device of claim 1 , wherein said second P+ region of said program/erase PMOS transistor and said third P+ region of said access PMOS transistor are formed in a common P+ region.
5. The memory device of claim 1 , wherein said floating gate comprises a doped polysilicon layer.
6. The memory device of claim 1 , wherein a gate capacitance of the control gate NMOS transistor is large compared to the gate capacitance of the program/erase PMOS transistor.
7. The memory device of claim 1 , further comprising a plurality of electrically-conductive bias lines extending along said word line direction, and wherein said fourth P+ region of said access PMOS transistor of each memory cell is electrically connected to a corresponding bias line.
8. The memory device of claim 7 , wherein said bias line is electrically connected in common to the fourth P+ region of each access transistor of said memory cells.
9. A memory cell, comprising: a program/erase PMOS transistor including a first gate, and first and second P+ regions formed within an n-doped well formed within a p-doped substrate, wherein said first P+ region is electrically connected to a corresponding bit line; an access PMOS transistor including a second gate, and third and fourth P+ regions formed within said n-doped well, wherein said third P+ region is electrically connected to said second P+ region of said program/erase PMOS transistor, and said second gate is electrically connected to a corresponding word line; and a control gate NMOS transistor formed in a p-doped pocket which, in turn, is formed in said n-doped well, wherein said control gate NMOS transistor comprises a third gate, and first and second N+ regions formed within said p-doped pocket, wherein said first and second N+ regions are electrically connected to a corresponding control gate line, and said third gate is electrically connected to said first gate of said program/erase PMOS transistor to form a floating gate.
10. The memory cell of claim 9 , wherein said first and second N+ regions are electrically connected to said corresponding control gate line by way of an electrically-conductive layer formed above said p-doped substrate.
11. The memory cell of claim 9 , further comprising a fifth P+ region formed within said p-doped pocket, wherein said fifth P+ region is electrically connected to said corresponding control gate line.
12. The memory cell of claim 9 , wherein said second P+ region of said program/erase PMOS transistor and said third P+ region of said access PMOS transistor are formed in a common P+ region.
13. The memory cell of claim 9 , wherein said floating gate comprises a doped polysilicon layer.
14. The memory cell of claim 9 , wherein a gate capacitance of the control gate NMOS transistor is large compared to the gate capacitance of the program/erase PMOS transistor.
15. The memory cell of claim 9 , wherein said fourth P+ region of said access PMOS transistor is electrically connected to a corresponding bias line.
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March 12, 2007
October 14, 2008
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