Disclosed is a NAND flash memory device comprising a memory cell array connected to a page buffer via a plurality of bitlines. The page buffer stores input data to be programmed in the memory cell array. The memory cell array is programmed by establishing bitline voltages for the plurality of bitlines according to the input data and then applying a wordline voltage to the memory cell array. The bitline voltages are established by first precharging the bitlines to a power supply voltage and then selectively discharging the bitlines according to the input data. The bitlines are discharged sequentially, i.e., some of the bitlines are discharged before others.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A NAND flash memory device, comprising: a memory cell array connected to a plurality of bitlines, wherein the plurality of bitlines is divided into N groups of bitlines, where “N” is an integer greater than 2; a page buffer storing input data to be programmed in the memory cell array and connected to the memory cell array via the plurality of bitlines; and, a bitline setup circuit connected to the bitlines and sequentially discharging the N groups of bitlines according to the input data during a single programming operation, wherein the bitline setup circuit comprises: N switch circuits respectively connecting/disconnecting the N groups of bitlines to/from the page buffer; and a control circuit controlling operation of the N switch circuits to sequentially discharge the N groups of bitlines through the page buffer.
2. The NAND flash memory device of claim 1 , wherein the switch circuit comprises switches respectively formed on each one of the plurality of bitlines.
3. The NAND flash memory device of claim 2 , wherein at least one of the switches comprises a negative metal oxide semiconductor (NMOS) transistor.
4. The NAND flash memory device of claim 1 , wherein the page buffer comprises: a first page buffer and a second page buffer formed on opposite sides of the cell array; and, wherein the bitline setup circuit comprises: a first bitline setup circuit setting up first bitlines within the N groups of bitlines connected between the memory cell array and the first page buffer; and, a second bitline setup circuit setting up second bitlines within the N groups of bitlines connected between the memory cell array and the second page buffer.
5. The NAND flash memory device of claim 4 , wherein the control circuit is configured to discharge the first bitlines after the second bitlines.
6. The NAND flash memory device of claim 1 , wherein the page buffer comprises: a plurality of latches storing the input data and connected to the plurality of bitlines.
7. A NAND flash memory device, comprising: a memory cell array comprising a plurality of bitlines divided into an alternating arrangement of even and odd bitlines, wherein the even bitlines are further divided into first, second, and third bitline groups; a page buffer storing input data to be programmed in the memory cell array and connected to the plurality of bitlines via a bitline setup circuit, wherein the bitline setup circuit comprises first, second, and third switch circuits connecting the first, second, and third bitline groups, respectively, to the page buffer; and a control circuit using the first through third switch circuits to sequentially discharge the first through third bitline groups, respectively, in accordance with the input data during a single programming operation.
8. The NAND flash memory device of claim 7 , wherein the page buffer comprises a plurality of latch circuits respectively associated with bitlines of the first through third bitline groups and adapted to store input data to be programmed in the memory cell array.
9. The NAND flash circuit of claim 8 , wherein the first switch circuit comprises: a first transistor switching a bitline of the first bitline group; a second transistor switching a first odd bitline the odd bitlines, wherein the outputs of the first and second transistors are connected to a first common output node; a first common node transistor connecting the first common output node and a first latch circuit of the plurality of latch circuits; another first transistor switching another bitline of the first bitline group; another second transistor switching a second odd bitline of the odd bitlines, wherein the outputs of the another first and second transistors are connected to a second common output node; and a second common node transistor connecting the second common output node and a second latch circuit of the plurality of latch circuits.
10. The NAND flash memory device of claim 9 , wherein the control circuit comprises first and second control circuits configured to respectively control the operation of the first and second switch circuits.
11. The NAND flash memory device of claim 10 , wherein the first control circuit generates a first control signal commonly applied to the gates of the first transistor and the another first transistor, a second control signal commonly applied to the gates of the second transistor and the another second transistor, and a third control signal applied to the gates of the first and second common node transistors.
12. The NAND flash circuit of claim 11 , wherein the second switch circuit comprises: a third transistor switching a bitline of the second bitline group; a fourth transistor switching a third odd bitline of the odd bitlines, wherein the outputs of the third and fourth transistors are connected to a third common output node; a third common node transistor connecting the third common output node and a third latch circuit of the plurality of latch circuits; another third transistor switching another bitline of the second bitline group; another fourth transistor switching a fourth odd bitline of the odd bitlines, wherein the outputs of the another third and fourth transistors are connected to a fourth common output node; and a fourth common node transistor connecting the fourth common output node and a fourth latch circuit of the plurality of latch circuits.
13. The NAND flash memory device of claim 12 , wherein the second control circuit generates a fourth control signal commonly applied to the gates of the third transistor and the another third transistor, a fifth control signal commonly applied to the gates of the fourth transistor and the another fourth transistor, and a sixth control signal applied to the gates of the third and fourth common node transistors.
14. The NAND flash memory device of claim 13 , wherein application of the first through sixth control signals to the bitline setup circuit sequentially discharges the first and second bitline groups in accordance with the input data.
15. A method of programming a NAND flash memory device, the method comprising: storing input data in a page buffer connected to a memory cell array through a plurality of bitlines, wherein the plurality of bitlines is divided into an alternating arrangement of even and odd bitlines, and wherein the even bitlines are further divided into first, second, and third bitline groups; during a single program operation, sequentially setting up bitline voltages for the first through third bitline groups; and thereafter, applying a program voltage to a selected wordline of the memory cell array.
16. The method of claim 15 , wherein sequentially setting up the bitline voltages for the first through third bitline groups comprises: pre-charging the plurality of bitlines to a power source voltage; and thereafter, sequentially discharging the first through third bitline groups based on the input data.
17. The method of claim 16 , wherein sequentially discharging the first through third bitline groups based on the input data comprises: discharging bitlines within the first through third bitline groups that are connected to latches storing a logical ‘0’ in the page buffer.
18. The method of claim 16 , wherein sequentially discharging the first through third bitline groups based on the input data comprises: maintaining bitlines within the first through third bitline groups that are connected to latches storing a logical ‘1’ in the page buffer at the power source voltage.
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October 4, 2005
October 28, 2008
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