Counter control signal generating circuit

1. A counter control signal generating circuit comprising: a first counter configured to receive a latched external address, and count the latched external address for a first latency, thereby generating a first counted address; a second counter configured to count the first counted address for a second latency, thereby generating a second counted address; a counter control signal generator configured to receive a write recognition signal, which is enabled in response to a write command, and generate a counter control signal for controlling enabling of the second counter, in response to the write recognition signal; a first detecting signal generator configured to receive the write recognition signal, generate a first command signal obtained after counting of the write recognition signal for the first latency, and generate a first detecting signal, which is enabled in response to the write recognition signal; and a second detecting signal generator configured to receive the first command signal, generate a second command signal obtained after counting of the first command signal for the second latency, and generate a second detecting signal, which is enabled in response to the first command signal.

2. The counter control signal generating circuit according to claim 1 , wherein the counter control signal is enabled in response to the first detecting signal and the second detecting signal.

3. The counter control signal generating circuit according to claim 1 , wherein at least one of the first and second detecting signals is maintained in an enable state until the second command signal is generated.

4. The counter control signal generating circuit according to claim 1 , wherein the counter control signal generator comprises: a first logic device configured to receive the write recognition signal and a first reset signal, and perform a first logical operation to the write recognition signal and the first reset signal; a second logic device configured to receive the first and second detecting signals, and perform a second logical operation to the first and second detecting signals; a first logic unit configured to receive an output signal from the second logic device and a second reset signal delayed from the first reset signal for a predetermined period, and perform a third logical operation to the output signal of the second logic device and the second reset signal; a latch unit configured to receive and latch an output signal from the first logic device and an output signal from the first logic unit; and a second logic unit configured to receive a signal delayed from an output signal from the latch unit for a predetermined period and an internal clock, and perform a fourth logical operation to the delayed signal and the internal clock, thereby generating the counter control signal.

5. The counter control signal generating circuit according to claim 1 , wherein the first detecting signal generator comprises: a latch unit comprising first to fourth latches, which are connected in series, to sequentially latch the write recognition signal in response to an internal clock; a command signal generator comprising a first transfer device for transferring the write recognition signal, as the first command signal, in response to a first latency signal, a second transfer device for transferring an output signal from the second latch, as the first command signal, in response to a second latency signal, and a third transfer device for transferring an output signal from the fourth latch, as the first command signal, in response to a third latency signal; a signal transfer unit comprising a first transfer unit for transferring an output signal from the first latch, in response to a first latency enable signal, and a second transfer unit for transferring an output signal from the third latch in response to a second latency enable signal; and a detecting signal generator configured to receive a signal obtained for buffering the write recognition signal and the signals transferred from the first and second transfer units, and perform a logical operation to the received signals, thereby generating the first detecting signal, wherein the first latency enable signal is enabled in response to the second or third latency signal, and the second latency enable signal is enabled in response to the third latency signal.

6. The counter control signal generating circuit according to claim 5 , wherein the first transfer unit comprises: a first logic device configured to receive the output signal from the first latch, a signal obtained after buffering the output signal from the second latch, and the first latency enable signal, and perform a first logical operation to the received signals; and a second logic device configured to receive the output signal from the first logic device and the first latency enable signal, and perform a second logical operation to the output signal of the first logic device and the first latency enable signal.

7. The counter control signal generating circuit according to claim 5 , wherein the second transfer unit comprises: a first logic device configured to receive the output signal from the third latch, a signal obtained after buffering the output signal from the fourth latch, and the second latency enable signal, and perform a first logical operation to the received signals; and a second logic device configured to receive the output signal from the first logic device and the second latency enable signal, and perform a second logical operation to the output signal of the first logic device and the second latency enable signal.

8. The counter control signal generating circuit according to claim 5 , further comprising: an enable signal generator configured to receive the first and second latency signals, and generate the first and second latency enable signals, wherein the enable signal generator comprises: a delay device for delaying the first latency signal for a predetermined period; a first buffer for buffering an output signal from the delay device, thereby generating the first latency enable signal; a logic unit configured to receive the output signal from the delay device and the second latency signal, and perform a logical operation to the received signals; and a second buffer for buffering an output signal from the logic unit, thereby generating the second latency enable signal.

9. The counter control signal generating circuit according to claim 1 , wherein the second detecting signal generator comprises: a latch unit comprising first to fourth latches, to sequentially latch the first command signal in response to an internal clock; a command signal generator comprising a first transfer device for transferring the first command signal, as the second command signal, in response to a first latency signal, a second transfer device for transferring an output signal from the second latch, as the second command signal, in response to a second latency signal, and a third transfer device for transferring an output signal from the fourth latch, as the second command signal, in response to a third latency signal; a signal transfer unit comprising a first transfer unit for transferring an output signal from the first latch, in response to a first latency enable signal, and a second transfer unit for transferring an output signal from the third latch in response to a second latency enable signal; and a detecting signal generator configured to receive a signal obtained for buffering the write recognition signal and the signals transferred from the first and second transfer units, and perform a logical operation to the received signals, thereby generating the second detecting signal, wherein the first latency enable signal is enabled in response to the second and third latency signals, and the second latency enable signal is enabled in response to the third latency signal.

10. The counter control signal generating circuit according to claim 9 , wherein the first transfer unit comprises: a first logic device configured to receive the output signal from the first latch, a signal obtained after buffering the output signal from the second latch, and the first latency enable signal, and perform a first logical operation to the received signals; and a second logic device configured to receive the output signal from the first logic device and the first latency enable signal, and perform a second logical operation to the output signal of the first logic device and the first latency enable signal.

11. The counter control signal generating circuit according to claim 9 , wherein the second transfer unit comprises: a first logic device configured to receive the output signal from the third latch, a signal obtained after buffering the output signal from the fourth latch, and the second latency enable signal, and perform a first logical operation to the received signals; and a second logic device configured to receive the output signal from the first logic device and the second latency enable signal, and perform a second logical operation to the output signal of the first logic device and the second latency enable signal.

12. The counter control signal generating circuit according to claim 9 , further comprising: an enable signal generator configured to receive the first and second latency signals, and generate the first and second latency enable signals, wherein the enable signal generator comprises: a delay device for delaying the first latency signal for a predetermined period; a first buffer for buffering an output signal from the delay device, thereby generating the first latency enable signal; a logic unit configured to receive the output signal from the delay device and the second latency signal, and perform a logical operation to the received signals; and a second buffer for buffering an output signal from the logic unit, thereby generating the second latency enable signal.

13. A counter control signal generating circuit comprising: a counter configured to count a first counted address for a predetermined latency, thereby generating a second counted address; a counter control signal generator configured to receive a write recognition signal, which is enabled in response to a write command, and generate a counter control signal for controlling enabling of the counter, in response to the write recognition signal; and a detecting signal generator configured to receive the write recognition signal, generate a command signal obtained after counting of the write recognition signal for the predetermined latency, and generate a detecting signal, which is enabled in response to the write recognition signal.

14. The counter control signal generating circuit according to claim 13 , wherein the counter control signal is enabled in response to the detecting signal.

15. The counter control signal generating circuit according to claim 13 , wherein the detecting signal is maintained in an enable state until the command signal is generated.

16. The counter control signal generating circuit according to claim 13 , wherein the counter control signal generator comprises: a first logic device configured to receive the write recognition signal and a first reset signal, and perform a first logical operation to the write recognition signal and the first reset signal; a second logic device configured to receive and buffer the detecting signal; a first logic unit configured to receive an output signal from the second logic device and a second reset signal delayed from the first reset signal for a predetermined period, and perform a second logical operation to the output signal of the second logic device and the second reset signal; a latch unit configured to receive and latch an output signal from the first logic device and an output signal from the first logic unit; and a second logic unit configured to receive a signal delayed from an output signal from the latch unit for a predetermined period and an internal clock, and perform a third logical operation to the delayed signal and the internal clock, thereby generating the counter control signal.

17. The counter control signal generating circuit according to claim 13 , wherein the detecting signal generator comprises: a latch unit comprising first to fourth latches, which are connected in series, to sequentially latch the write recognition signal in response to an internal clock; a command signal generator comprising a first transfer device for transferring the write recognition signal, as the command signal, in response to a first latency signal, a second transfer device for transferring an output signal from the second latch, as the command signal, in response to a second latency signal, and a third transfer device for transferring an output signal from the fourth latch, as the command signal, in response to a third latency signal; a signal transfer unit comprising a first transfer unit for transferring an output signal from the first latch, in response to a first latency enable signal, and a second transfer unit for transferring an output signal from the third latch in response to a second latency enable signal; and a detecting signal generation unit configured to receive a signal obtained for buffering the write recognition signal and the signals transferred from the first and second transfer units, and perform a logical operation to the received signals, thereby generating the detecting signal, wherein the first latency enable signal is enabled in response to the second or third latency signal, and the second latency enable signal is enabled in response to the third latency signal.

18. The counter control signal generating circuit according to claim 17 , wherein the first transfer unit comprises: a first logic device configured to receive the output signal from the first latch, a signal obtained after buffering the output signal from the second latch, and the first latency enable signal, and perform a first logical operation to the received signals; and a second logic device configured to receive the output signal from the first logic device and the first latency enable signal, and perform a second logical operation to the output signal of the first logic device and the first latency enable signal.

19. The counter control signal generating circuit according to claim 17 , wherein the second transfer unit comprises: a first logic device configured to receive the output signal from the third latch, a signal obtained after buffering the output signal from the fourth latch, and the second latency enable signal, and perform a first logical operation to the received signals; and a second logic device configured to receive the output signal from the first logic device and the second latency enable signal, and perform a second logical operation to the output signal of the first logic device and the second latency enable signal.

20. The counter control signal generating circuit according to claim 17 , further comprising: an enable signal generator configured to receive the first and second latency signals, and generate the first and second latency enable signals, wherein the enable signal generator comprises: a delay device for delaying the first latency signal for a predetermined period; a first buffer for buffering an output signal from the delay device, thereby generating the first latency enable signal; a logic unit configured to receive the output signal from the delay device and the second latency signal, and perform a logical operation to the received signals; and a second buffer for buffering an output signal from the logic unit, thereby generating the second latency enable signal.