Semiconductor memory device and method for driving bit line sense amplifier thereof

1. A semiconductor memory device, comprising: an amplifying unit for amplifying a voltage difference between a bit line pair; a power supply driver for supplying a power to the amplifying unit in response to a second driving signal; a control unit for generating a first driving signal of the power supply driver in response to an amplifying unit enable signal; a selection signal generation unit for generating a plurality of selection signals for determining a turning-on transition speed of the power supply driver; a power supply driver driving unit for generating the second driving signal according to the first driving signal and the plurality of selection signals; wherein the power supply driver driving unit includes; a plurality of logic combination units, each logic combination unit performing a logic operation with a corresponding selection signal and the first driving signal; and a power driving unit for receiving the first driving signal to drive an output node, wherein the selection signal generation unit includes: a test mode enable signal generation unit for generating a test mode enable signal in order to perform a test operation; a fuse unit for generating a fuse signal according to cutting or not cutting of a fuse; and an output unit for activating the plurality of selection signals when at least one of the test mode enable signal and the fuse signal is activated.

2. The semiconductor memory device as recited in claim 1 , wherein the power supply driver driving unit includes: the output node for outputting the second driving signal; and a plurality of drivers for driving the output node according to outputs of the plurality of logic combination units.

3. The semiconductor memory device as recited in claim 2 , wherein the plurality of drivers includes: a first driver driven by the first driving signal; and at least one second driver driven according to the first driving signal and each logic state of the plurality of selection signals.

4. The semiconductor memory device as recited in claim 1 , wherein the fuse signal is activated by a fuse cutting of the fuse unit.

5. A semiconductor memory device, comprising: an amplifying unit for amplifying a voltage difference between a bit line pair; a first power supply driver for supplying a first power supply voltage to the amplifying unit; a second power supply driver for supplying a second power supply voltage to the amplifying unit; a control unit for generating a first driving signal of the first power supply driver and a first driving signal of the second power supply driver in response to an amplifying unit enable signal; a first selection signal generation unit for generating a plurality of first selection signals for determining a turning-on transition speed of the first power supply driver; a second selection signal generation unit for generating a plurality of second selection signals for determining a turning-on transition speed of the second power supply driver; a first power supply driver driving unit for generating a second driving signal of the first power supply driver according to the first driving signal of the first power supply driver and the plurality of first selection signals and for supplying the second driving signal to the first power supply driver, wherein the first power supply driver driving unit includes a plurality of first logic combination units, each of the first logic combination units performing a logic operation with a corresponding first selection signal and the first driving signal of the first power supply driver, and a first power driving unit for receiving the first driving signal of the first power supply driver to drive a first output node; and a second power supply driver driving unit for generating a second driving signal of the second power supply driver according to the first driving signal of the second power supply driver and the plurality of second selection signals and for supplying the second driving signal to the second power supply driver, wherein the second power supply driver driving unit includes a plurality of second logic combination units, each of the second logic combination units performing a logic operation with a corresponding second selection signal and the first driving signal of the second power supply driver, and a second power driving unit for receiving the first driving signal of the second power supply driver to drive a second output node, wherein the first selection signal generation unit includes: a test mode enable signal generation unit for generating a test mode enable signal in order to perform a test operation; a fuse unit for generating a fuse signal according to cutting or not cutting of a fuse; and an output unit for activating the first selection signal when at least one of the test mode enable signal and the fuse signal is activated.

6. The semiconductor memory device as recited in claim 5 , wherein the first power supply driver driving unit includes: the first output node for outputting the second driving signal of the first power supply driver; and a plurality of pull-down drivers for driving the first output node according to outputs of the plurality of first logic combination units.

7. The semiconductor memory device as recited in claim 6 , wherein the plurality of pull-down drivers includes: a first pull-down driver driven by the first driving signal of the first power supply driver; and at least one second pull-down driver driven according to the first driving signal of the first power supply driver and each logic state of the plurality of first selection signals.

8. The semiconductor memory device as recited in claim 5 , wherein the second power supply driver driving unit includes: the second output node for outputting the second driving signal of the second power supply driver; and a plurality of pull-up drivers for driving the second output node according to outputs of the plurality of second logic combination units.

9. The semiconductor memory device as recited in claim 8 , wherein the plurality of pull-up drivers includes: a first pull-up driver driven by the first driving signal of the second power supply driver; and at least one second pull-up driver driven according to the first driving signal of the second power supply driver and each logic state of the plurality of second selection signals.

10. The semiconductor memory device as recited in claim 5 , wherein the fuse signal is activated by a fuse cutting of the fuse unit.

11. The semiconductor memory device as recited in claim 5 , wherein the second selection signal generation unit includes: a test mode enable signal generation unit for generating a test mode enable signal in order to perform a test operation; a fuse unit for generating a fuse signal according to cutting or not cutting of a fuse; and an output unit for activating the second selection signal when at least one of the test mode enable signal and the fuse signal is activated.

12. The semiconductor memory device as recited in claim 11 , wherein the fuse signal is activated by a fuse cutting of the fuse unit.

13. The semiconductor memory device as recited in claim 5 , wherein the first power supply voltage is a power supply voltage (VDD) of the semiconductor memory device.

14. The semiconductor memory device as recited in claim 5 , wherein the second power supply voltage is a ground voltage (VSS).

15. The semiconductor memory device as recited in claim 5 , wherein the first power supply driver driving unit includes: a first inverter for receiving the first driving signal of the first power supply driver; a second inverter for receiving an output of the first inverter; a plurality of third inverters for respectively receiving the plurality of first selection signals; a plurality of NOR gates for respectively receiving outputs of the plurality of third inverters and the output of the first inverter; a PMOS transistor for receiving an output of the second inverter through a gate of the PMOS transistor; a first NMOS transistor for receiving an output of the second inverter through a gate of the first NMOS transistor; a plurality of second NMOS transistors whose gates respectively receive outputs of the plurality of NOR gates; and an output node commonly coupled by the PMOS transistor, the first and the plurality of second NMOS transistors.

16. The semiconductor memory device as recited in claim 15 , wherein each number of the third inverters, the NOR gates and the second NMOS transistors is equal to the number of the plurality of first selection signals.

17. The semiconductor memory device as recited in claim 5 , wherein the second power supply driver driving unit includes: a plurality of NAND gates for respectively receiving the plurality of second selection signals and the first driving signal of the second power supply driver; an inverter for receiving the first driving signal of the second power supply driver; an NMOS transistor for receiving an output of the inverter through a gate of the NMOS transistor; a first PMOS transistor for receiving the output of the inverter through a gate of the first PMOS transistor; a plurality of second PMOS transistors whose gates respectively receive outputs of the plurality of NAND gates; and an output node commonly coupled by the NMOS transistor, the first and the plurality of second PMOS transistors.

18. The semiconductor memory device as recited in claim 17 , wherein each number of the NAND gates and the plurality of second PMOS transistors is equal to the number of the plurality of second selection signals.

19. The semiconductor memory device as recited in claim 5 , wherein the output unit includes: a NOR gate for receiving the test mode enable signal and the fuse signal; and an inverter for inverting an output of the NOR gates to thereby generate the first selection signal.

20. The semiconductor memory device as recited in claim 11 , wherein the output unit includes: a NOR gate for receiving the test mode enable signal and the fuse signal; and an inverter for inverting an output of the NOR gates to thereby generate the second selection signal.

21. A method for operating a semiconductor memory device, comprising the steps of: a) generating a first driving signal in response to an amplifying unit enable signal; b) generating a plurality of first selection signals for determining a turning-on transition speed of a first power supply driver which supplies a first power supply voltage to an amplifying unit and generating a plurality of second selection signals for determining a turning-on transition speed of a second power supply driver which supplies a second power supply voltage to the amplifying unit, wherein the first selection signals and the second selection signals are activated respectively when at least one of a test mode enable signal and a fuse signal is activated; c) generating a plurality of second selection signals for determining a turning-on transition speed of a second power supply driver which supplies a second power supply voltage to the amplifying unit; d) performing a plurality of logic operations, each of the plurality of logic operations performing with corresponding one of the first selection signals and the first driving signal; e) performing a plurality of logic operations, each of the plurality of logic operations performing with corresponding one of the second selection signals and the first driving signal; f) supplying a second driving signal of the first power supply driver to the first power supply driver in response to the first driving signal and the plurality of first selection signals and supplying a second driving signal of the second power supply driver to the second power supply driver in response to the first driving signal and the plurality of second selection signals; g) supplying the first and the second power supply voltages to the amplifying unit; and h) amplifying a voltage difference between a bit line pair.

22. The method as recited in claim 21 , wherein the first the first power supply voltage is a power supply voltage (VDD) of the semiconductor memory device.

23. The semiconductor memory device as recited in claim 21 , wherein the second power supply voltage is a ground voltage (VSS).