Peripheral input and output buffer circuitry is tested using scan path circuitry selectively connecting external signals TSA, TSB, and TSC to the buffer circuitry. This is in addition to testing the internal circuitry of the integrated circuit with the scan path circuitry. An external signal, TSC, provides a load to the output of the buffer circuitry. An external signal, TSA, receives a response from input buffer circuitry and supplies a stimulus signal to output buffer circuitry. An external signal, TSB, receives a response signal from output buffer circuitry and supplies a stimulus signal to input buffer circuitry. This avoids a wafer tester having to contact bond pads connected to the buffer circuitry.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit providing test pads in addition to scan circuitry comprising: A. core circuitry having a core output lead; B. boundary scan circuitry having a boundary input lead connected to the core output lead and a boundary output lead; C. a bond pad; D. an output buffer having an input lead coupled to the boundary output lead and having an output lead connected to the bond pad; E. a first test signal lead connected to a first test pad; F. a second test signal lead connected to a second test pad; G. a third test signal lead connected to a third test pad; and H. peripheral scan circuitry having a peripheral scan path including scannable cells controlling switches: i. a first switch selectively connecting the first test signal lead to the input lead of the output buffer; ii. a second switch selectively connecting the second test signal lead to the output lead of the output buffer; and iii. a third switch selectively connecting the third signal lead to the output of the output buffer.
2. The integrated circuit of claim 1 including test access port circuitry that includes the boundary scan circuitry, the peripheral scan circuitry, a test clock input pad, a test mode select input pad, a test reset input pad, a test data input pad, and a test data output pad.
3. The integrated circuit of claim 1 in which the first switch has a switch input connected to the first test signal lead, a switch output connected to the input of the output buffer, and a control input connected with the peripheral scan circuitry.
4. The integrated circuit of claim 1 in which the second switch has a switch input connected to the second test signal lead, a switch output connected to the output of the output buffer, and a control input connected with the peripheral scan circuitry.
5. The integrated circuit of claim 1 in which the third switch has a switch input connected to the second test signal lead, a switch output connected to the output of the output buffer, and a control input connected with the peripheral scan circuitry.
6. The integrated circuit of claim 1 including electrostatic discharge protection circuitry connected to the input of the input buffer and the output of the output buffer between the third and fourth switches and the input buffer and the output of the output buffer.
7. The integrated circuit of claim 1 including bus holding circuitry connected to the input of the input buffer and the output of the output buffer between the third and fourth switches and the input buffer and the output of the output buffer.
8. The integrated circuit of claim 1 in which the boundary scan circuitry has an input connected to the output of the output buffer.
9. The integrated circuit of claim 1 including electrostatic discharge circuitry connected to the output of the output buffer between the output buffer and the bond pad, the second switch, and the third switch.
10. The integrated circuit of claim 9 including bus holder circuitry connected to the output of the output buffer between the output buffer and the electrostatic discharge circuitry.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 7, 2007
November 11, 2008
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