A semiconductor device package is provided which can achieve speeding-up thereof. The semiconductor device package includes: a board which has at least one of a ground plane and a power plane; at least one connecting conductor portion which is formed on an inner wall surface of an opening portion of the board and electrically connected to the corresponding plane; at least one bonding pattern which is formed on a front surface layer portion of the board in the vicinity of an edge of the opening portion, and connected to the corresponding connecting conductor portion; and a second external connection portion which is formed on the side of the front surface layer of the board, and electrically connected to the corresponding plane, respectively, through a through-hole conductor portion formed in the board.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device package, comprising: a board including at least one of a ground plane and a power plane; a wiring pattern which is formed on a side of a front surface of the board; a first external connection portion connecting the wiring pattern externally which is formed on the front surface side of the board; an opening portion formed in the board; at least one connecting conductor portion which is formed on an inner wall of the opening portion, and electrically connected to the corresponding one of said at least one of the ground plane and the power plane; at least one bonding pattern which is formed on the front surface side of the board, and connected to the corresponding connecting conductor portion; a second external connection portion which is formed on the front surface side of the board, and electrically connected to the corresponding one of said at least one of the ground plane and the power plane through a through-hole conductor portion formed in the board; a semiconductor chip mounted on a side of a back surface of the board, the semiconductor chip having a first terminal portion and a second terminal portion both facing the opening portion; a first wire for electrically connecting the wiring pattern and the first terminal portion through the opening portion; and a second wire for electrically connecting the bonding pattern and the second terminal portion through the opening portion.
2. The semiconductor device package according to claim 1 , further comprising: a concave groove formed in the inner wall of the opening portion, wherein the connecting conductor portion is formed on a wall surface of the concave groove.
3. The semiconductor device package according to claim 1 , further comprising: bumps formed on the first external connection portion and the second external connection portion.
4. The semiconductor device package according to claim 1 , wherein said at least one of the ground plane and the power plane is formed in an internal layer of the board.
5. The semiconductor device package according to claim 1 , wherein one of the ground plane and the power plane is formed on a side of a back surface of the board.
6. The semiconductor device package according to claim 1 , further comprising: a concave groove formed in the inner wall of the opening portion, wherein the connecting conductor portion is formed on the inner wall of the opening portion where the concave groove is not formed.
7. The semiconductor device package according to claim 1 , wherein said at least one connecting conductor portion comprises a plurality of connecting conductor portions respectively and electrically connected to the corresponding one of said at least one of the ground plane and the power plane.
8. The semiconductor device package according to claim 1 , wherein the semiconductor chip, the first wire and the second wire are sealed with a sealing resin.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 15, 2006
November 18, 2008
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