Efficient memory update process for on-the-fly instruction translation for well behaved applications executing on a weakly-ordered processor

1. A method for improving processing efficiency of operations of a well-behaved application executing on a weakly-ordered processor, said method comprising: in a weakly-ordered processor executing a well-behaved application, first determining a value of a lock flag within the weakly-ordered processor, wherein the lock flag is one of two values with a first value indicating that sync instructions are to be issued after each store operation and before issuance of a next, subsequent store operation, and a second value indicating that sync instructions are not to be issued after each store operation during a lock phase, wherein issuance of a sync instruction after a store operation causes the store operation to be completed before a subsequently issued store operation is completed, so that all store operations are completed in sequential order of issuance; when the lock flag is set the first value, issuing sync instructions after each store operation of the well-behaved application; when the lock flat is set to the second value: tracking an address of a lock when the lock is initially obtained at the processor, wherein said tracking of an address of a lock comprises storing the address in a link-list of lock addresses; determining when a subsequent store instruction issued from the processor is an unlock instruction, wherein said subsequent store instruction is an unlock instruction when the subsequent store instruction targets the address of the lock and wherein all other subsequent store instructions issued before the unlock instruction are intermediate stores that are executed without requiring issuance of a sync instruction after each store and which do not affect the lock obtained by the processor; wherein said determining comprises checking an address of the store instruction against the link-list of lock addresses for a match; withholding the issuance of a synchronization (sync) instruction following the store instruction when the store instruction is not the unlock instruction, wherein the issuance of a sync instruction is withheld after each intermediate store operation that is not the unlock instruction; and responsive to the determining, generating and issuing a sync instruction prior to executing the unlock instruction, wherein said sync instruction makes updates generated by the intermediate stores visible at a point of coherency before executing the unlock instruction; wherein a single sync instruction is issued prior to the unlock instruction to synchronize all intermediate stores at the point of coherence.

2. The method of claim 1 , wherein the point of coherency is a lower level cache visible to each processor within a multiprocessor data processing system in which said weakly-ordered processor is operating.

3. The method of claim 1 , further comprising flushing all data generated by said intermediate stores out to the point of coherency.

4. The method of claim 1 , wherein: said tracking of an address of a lock comprises storing the address in a table of lock addresses; and said determining comprises checking an address of the store instruction against the table of lock addresses for a match.