A stackable semiconductor package includes a substrate with a first side surface that includes circuit patterns. Each circuit pattern includes a pad. A semiconductor die is electrically coupled to the circuit patterns. An encapsulant covers the semiconductor die and the first side surface of the substrate inward of the pads. A layer of a solder is fused to each of the pads. A lateral distance between immediately adjacent pads is selected to be greater than a lateral distance between sidewalls of the encapsulant and immediately adjacent pads, and a height of the solder layers relative to the first side surface is selected to be less than a height of the sidewalls of the encapsulant, so that misalignment of a semiconductor package stacked on the solder layers/pads is self-correcting when juxtaposed ones of the solder layers and respective solder balls of the second semiconductor package are reflowed and fused together.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming a stack of semiconductor packages comprising: coupling a semiconductor die to a substrate, the substrate comprising a first side surface including metal first circuit patterns, and a second side surface opposite the first side surface and including metal second circuit patterns, wherein each of the first circuit patterns includes a respective one of a plurality of first pads, the first pads are aligned in a plurality of rows, each of the first pads is a lateral distance “a” from immediately adjacent ones of the first pads, and at least some of the first circuit patterns are electrically coupled through the substrate to at least some of the second circuit patterns; covering the semiconductor die and a portion of the first side surface of the substrate with an encapsulant, wherein the encapsulant has substantially vertical sidewalls extending a vertical distance “d” from the first side surface of the substrate, all of the first pads are external to the encapsulant, and each of the first pads that is immediately adjacent to one of the sidewalls of the encapsulant is a lateral distance “b” from the respective sidewall; and forming a plurality of layers of a solder on the first pads, wherein each of the layers of the solder has an exposed exterior surface portion that faces in a same direction as the first side surface of the substrate and extends a maximum vertical distance “c” from the first side surface of the substrate, and wherein a>b and c<d.
2. The method of forming a stack of semiconductor packages of claim 1 , wherein each of the layers of the solder is substantially cylindrical.
3. The method of forming a stack of semiconductor packages of claim 1 , wherein the exposed exterior surface portion of each of the layers of the solder is arced.
4. The method of forming a stack of semiconductor packages of claim 1 , wherein each of the layers of the solder has the form of a trapezoidal prism.
5. The method of forming a stack of semiconductor packages of claim 1 , wherein each of the layers of the solder has a polymer core.
6. The method of forming a stack of semiconductor packages of claim 1 , wherein the encapsulant has four of the sidewalls that are arranged so that the encapsulant has a substantially rectangular lateral perimeter, and at least two of the sidewalls are parallel to and immediately adjacent to respective ones of the rows of the first pads.
7. The method of forming a stack of semiconductor packages of claim 6 , wherein each of the four sidewalls of the encapsulant is parallel to and immediately adjacent to a respective one of the rows of the first pads.
8. The method of forming a stack of semiconductor packages of claim 1 , further comprising forming a layer of a hardened insulative material covering the first side surface of the substrate between and around the first pads, wherein the layer of the hardened insulative material covers a portion of each of the layers of solder, but the exposed exterior surface of each of the layers of solder is outward of the layer of the hardened insulative material.
9. The method of forming a stack of semiconductor packages of claim 1 wherein the semiconductor die is coupled to the substrate in a flip chip connection.
10. The method of forming a stack of semiconductor packages of claim 9 further comprising coupling an underfill material between an active surface of the semiconductor die and the substrate.
11. The method of forming a stack of semiconductor packages of claim 1 wherein each of the second circuit patterns includes a respective one of a plurality of second pads, the method further comprising forming a plurality of layers of a solder on the second pads.
12. The method of forming a stack of semiconductor packages of claim 1 wherein the substrate is one of a plurality of substrates of a substrate sheet, the method further comprising singulating the substrate sheet.
13. The method of forming a stack of semiconductor packages of claim 1 , wherein the substrate is one of a plurality of substrates of a substrate sheet, the method further comprising: coupling bond wires between bond pads of the semiconductor die and bond fingers of the first circuit patterns; coupling first solder balls to the first pads of the first circuit patterns; reflowing the first solder balls to form the layers of the solder; coupling second solder balls to second pads of the second circuit patterns; fusing the second solder balls to the second pads of the second circuit patterns; and singulating the substrate sheet to form a stackable semiconductor package.
14. The method of forming a stack of semiconductor packages of claim 13 further comprising: placing a second semiconductor package on the stackable semiconductor package, wherein the second semiconductor package is laterally skewed.
15. The method of forming a stack of semiconductor packages of claim 14 wherein solder balls of the second semiconductor package are misaligned with the layers of the solder of the stackable semiconductor package.
16. The method of forming a stack of semiconductor packages of claim 15 wherein an inner row of the solder balls of the second semiconductor package rests between an inner row of the layers of the solder and one of the sidewalls of the encapsulant.
17. The method of forming a stack of semiconductor packages of claim 15 wherein an inner row of the solder balls of the second semiconductor package is caught against one of the sidewalls of the encapsulant.
18. The method of forming a stack of semiconductor packages of claim 15 further comprising reflowing the solder balls of the second semiconductor package, wherein the second semiconductor package is pulled into alignment with the stackable semiconductor package during the reflowing the solder balls of the second semiconductor package.
19. The method of forming a stack of semiconductor packages of claim 18 wherein the reflowing the solder balls of the second semiconductor package forms solder joints from the layers of the solder layers and the solder balls of the second semiconductor package.
20. A method of forming a stack of semiconductor packages comprising: coupling a semiconductor die to a first side surface of a substrate, the first side surface comprising metal first circuit patterns, wherein each of the first circuit patterns includes a respective one of a plurality of first pads, and the first pads are aligned into at least two parallel rows; covering the semiconductor die and a portion of the first side surface of the substrate with an enclosure without covering any of the first pads, wherein the enclosure has opposed parallel substantially vertical first and second sidewalls, wherein each of the first and second sidewalls is immediately adjacent to and parallel to a respective one of the rows of the first pads; forming a plurality of layers of a solder on the first pads, wherein each of the layers of the solder has an exposed exterior surface portion that faces in a same direction as the first side surface of the substrate, and wherein a lateral distance “a” between immediately adjacent ones of the first pads, a lateral distance “b” between each of the first and second sidewalls and the first pads of the row immediately adjacent to the respective sidewall, a vertical distance “c” between the first side surface and an uppermost portion of the exterior surface portion of each of the layers of the solder, and a vertical distance “d” between the first side surface and an uppermost edge of each of the first and second sidewalls of the enclosure are selected so that a>b and c<d.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 19, 2005
December 2, 2008
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