A multiplicity of synchronized inverters for driving a multiplicity of loads such as CCFLs that require high ac voltages are arranged in close proximity of the respective loads and controlled in phase. A frequency determination capacitor and a frequency determination resistor are connected to one of the inverters to generate a triangular wave signal and a clock signal. The triangular wave signal and clock signal thus generated are supplied to other inverters to synchronize all the loads so that they can be controlled in phase. The resistance of the frequency determination resistor is set to a substantially small magnitude at the time of startup to increase the frequency of the triangular wave signal, thereby enabling quick startup of the loads.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A parallel operating system of operating in parallel a multiplicity (N) of controller ICs, each controller IC comprising: an oscillator block for generating a triangular wave signal and a clock signal when connected to a frequency determination capacitor and a first frequency determination resistor, a logic block receiving said clock signal and outputting a signal obtained by frequency-dividing said clock signal; a first external terminal connected to said frequency determination capacitor and adapted to serve as an output terminal when said triangular wave signal is generated, but serve as an output terminal for receiving an external triangular wave signal when said triangular wave signal is not generated; a second external terminal connected to said first frequency determination resistor; a third external terminal adapted to serve as an input terminal of a startup signal; and a mode circuit for outputting signal, which enables said oscillator block and said logic block when said first frequency determination resistor is connected to said second external terminal, and which disables said oscillator and said logic block when said first frequency determination resistor is not connected.
2. A parallel operating system according to claim 1 , wherein said oscillator block generates a clock signal synchronize with said triangular wave signal; and allow said clock signal from the oscillator block associated with said one controller IC; and supply said clock signal generated by said one controller IC to the rest of said N controller ICs, whereby said N controller ICs are synchronized to said clock signal in performing in-phase PWM control of said N controller ICs.
3. The parallel operating system according to claim 2 , wherein said triangular wave signal and clock signal generated in said oscillator block have the same frequency; and said controller IC generating said triangular wave signal is adapted to generate a synchronization signal having a stepped-down frequency and supply said synchronization signal to the rest of said N controller ICs for use in common for synchronization thereof.
4. The parallel operating system according to claim 3 , wherein said synchronization signal has a stepped-down frequency obtained by frequency-dividing said clock signal by 2.
5. The parallel operating system according to claim 1 , wherein said triangular wave signal is generated at the node to which said frequency determination capacitor is connected, or a triangular wave signal generated by another controller IC is supplied.
6. The parallel operating system according to claim 1 , further comprising: a first comparator for comparing said startup signal with a first reference signal; a transistor having a gate receiving an output signal from said first comparator; and a source connected to a fixed potential node; a fourth external terminal connected to a drain of said transistor, wherein a second frequency determination resistor is connected between said fourth external terminal and said second external terminal; wherein during the startup, by turning on said transistor to set the frequency determination resistance connected to said second external terminal small, frequency of said triangular signal and said clock signal is set high.
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May 2, 2007
December 30, 2008
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