A hybrid dual match line circuit may include a hit match line coupled to a first group of load devices and a miss match line coupled to discharge through a second group of load devices. Both the hit and miss match lines may be configured to be precharged to an asserted state. Each of the second group of load devices may be activated for discharging by a respective miss signal. The hit match line may be additionally coupled to discharge through first and second discharge path respectively activated for discharging in response to a hit signal and a read/write enable signal. The hit and miss match lines may be electrically isolated from one another, such that when one or more of the respective miss signals are asserted, current from the hit match line does not discharge through the miss match line.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A dual match line circuit, comprising: a hit match line coupled to a first plurality of load devices and configured to be precharged to an asserted state; and a miss match line coupled to discharge through a second plurality of load devices and configured to be precharged to said asserted state, wherein each of said second plurality of load devices is activated for discharging by a respective miss signal; wherein said hit match line is additionally coupled to discharge through a first discharge path activated for discharging in response to a hit signal and to discharge through a second discharge path activated for discharging in response to a read/write enable signal; wherein said hit match line and said miss match line are electrically isolated from one another, such that when one or more of said respective miss signals are asserted, current from said hit match line does not discharge through said miss match line.
2. The dual match line circuit as recited in claim 1 , wherein said first discharge path comprises a pair of devices connected in series, wherein a first one of said pair of devices is activated for discharging in response to said hit signal, and wherein a second one of said pair of devices is activated for discharging in response to said miss match line being in said asserted state.
3. The dual match line circuit as recited in claim 1 , wherein each of said first plurality of load devices is respectively configured in a deactivated state as a dummy load device.
4. The dual match line circuit as recited in claim 1 , wherein said hit match line is coupled to an evaluate node via a coupling device, wherein said coupling device, when activated, is coupled to discharge said evaluate node through said hit match line.
5. The dual match line circuit as recited in claim 4 , wherein said coupling device is activated for discharging by a voltage difference between said hit match line and said miss match line, wherein said voltage difference is in excess of a threshold value.
6. The dual match line circuit as recited in claim 4 , further comprising an output driver coupled to said evaluate node and configured to output a global match signal.
7. The dual match line circuit as recited in claim 6 , wherein said global match signal is deasserted in a default state, and wherein said output driver is configured to assert said global match signal in response to said evaluate node discharging.
8. A content-addressable memory (CAM), comprising: a plurality of tag entries each configured to store a corresponding tag value; and a plurality of data entries each corresponding respectively to said tag entries and each configured to store a corresponding data value; wherein a given one of said tag entries includes: the dual match line circuit as recited in claim 1 ; and a plurality of bit cells coupled to said dual match line circuit, each configured to store a respective bit of said corresponding tag value and to compare said stored bit with a corresponding bit of an input tag value; wherein a first one of said plurality of bit cells is configured to output said hit signal, and wherein remaining ones of said plurality of bit cells are configured to respectively output said miss signals.
9. The content-addressable memory as recited in claim 8 , further comprising a decoder configured to decode an input read/write address value and, in response to determining that said input read/write address value corresponds to a given one of said data entries that corresponds respectively to said given tag entry, further configured to assert said read/write enable signal for activation of said second discharge path.
10. A processor, comprising: the content-addressable memory as recited in claim 8 ; and a functional unit coupled to said content-addressable memory, wherein said functional unit is configured to provide said input tag value to said content-addressable memory.
11. A system, comprising: the processor as recited in claim 10 ; and a system memory coupled to said processor.
12. A cache, comprising: a cache way including a plurality of cache lines, wherein each line includes a data value that corresponds to a cache tag value; comparison logic configured to perform a bitwise comparison between a cache tag value corresponding to a selected one of said plurality of cache lines and an input tag value; and the dual match line circuit as recited in claim 1 coupled to said comparison logic; wherein said comparison logic is further configured to produce said hit signal and said plurality of miss signals, and wherein said dual match line circuit is configured to indicate whether said input tag value matches said cache tag value corresponding to said selected cache line.
13. A processor, comprising: the cache as recited in claim 12 ; and a functional unit configured to determine a memory address including said input tag value and to convey said memory address to said cache.
14. A system, comprising: the processor as recited in claim 13 ; and a system memory coupled to said processor.
15. A comparator, comprising: the dual match line circuit as recited in claim 1 ; and a plurality of bitwise comparison circuits coupled to said dual match line circuit, wherein each bitwise comparison circuit is configured to compare corresponding bits of two or more input operands, wherein a first one of said bitwise comparison circuits is configured to output said hit signal, and wherein remaining ones of said plurality of bitwise comparison circuits are configured to respectively output said miss signals.
16. A processor, comprising: the comparator as recited in claim 15 ; and a functional unit configured to provide said input operands to said comparator.
17. A system, comprising: the processor as recited in claim 16 ; and a system memory coupled to said processor.
18. A method, comprising: precharging each of a hit match line, a miss match line and an evaluate node to an asserted state, wherein said hit match line is coupled to said evaluate node via a coupling device, and wherein said hit match line is additionally coupled to a first plurality of load devices; in response to detecting assertion of a hit signal, discharging said hit match line through a first discharge path; in response to detecting assertion of a read/write enable signal, discharging said hit match line through a second discharge path; in response to detecting assertion of one or more of a plurality of miss signals, discharging said miss match line through one or more of a second plurality of load devices, wherein each of said second plurality of load devices is activated for discharging by a respective one of said plurality of miss signals; wherein said hit match line and said miss match line are electrically isolated from one another, such that when one or more of said miss signals are asserted, current from said hit match line does not discharge through said miss match line.
19. The method as recited in claim 18 , wherein said first discharge path comprises a pair of devices connected in series, wherein a first one of said pair of devices is activated for discharging in response to said hit signal, and wherein a second one of said pair of devices is activated for discharging in response to said miss match line being in said asserted state.
20. A dual match line circuit, comprising: a hit match line coupled to a first plurality of load devices and configured to be precharged to an asserted state; and a miss match line coupled to discharge through a second plurality of load devices and configured to be precharged to said asserted state, wherein each of said second plurality of load devices is activated for discharging by a respective miss signal; wherein said hit match line is additionally coupled to discharge through a first discharge path and a second discharge path, wherein said first discharge path is activated for discharging in response both to assertion of a hit signal and said miss match line being in said asserted state, and wherein said second discharge path is activated for discharging in response to assertion of a read/write enable signal; wherein said hit match line and said miss match line are electrically isolated from one another, such that when one or more of said respective miss signals are asserted, current from said hit match line does not discharge through said miss match line.
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April 2, 2007
January 6, 2009
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