An apparatus for reducing leakage currents of an integrated circuit having at least one transistor, wherein the at least one transistor is connected between a supply potential and a first reference potential, the apparatus including a controller for controlling the first reference potential in dependence on the supply potential.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus for reducing a leakage current of an integrated circuit comprising at least one transistor connected between a supply potential and a first reference potential, comprising: a controller configured to control the first reference potential in dependence on the supply potential, such that a difference between the supply potential and the first reference potential is maintained at a substantially constant value equal to or higher than a required minimum data retention voltage.
2. The apparatus according to claim 1 , wherein the apparatus further comprises a selector configure to select the first or a second reference potential as reference potential for the at least one transistor, wherein the first reference potential lies in amount between the second reference potential and the supply potential.
3. The apparatus according to claim 1 , wherein the at least one transistor is part of an SRAM memory device.
4. The apparatus according to claim 2 , wherein the selector is configured to select the second reference potential for a normal operation of an SRAM memory device and select the first reference potential for an energy-saving mode of the SRAM memory device.
5. The apparatus according to claim 1 , wherein the at least one transistor is an NMOS transistor.
6. An apparatus for leakage current reduction for an integrated circuit comprising at least one transistor, comprising: a reference potential regulator comprising a first input for a supply potential, a second input for a reference potential, a terminal for a first reference potential to be regulated in dependence on the supply potential, such that a difference between the supply potential and the first reference potential is maintained at a substantially constant value equal to or higher than a required minimum data retention voltage, and a terminal for a second reference potential, wherein the at least one transistor is connected between the supply potential and the first reference potential.
7. The apparatus for leakage current reduction according to claim 6 , wherein the apparatus for leakage current reduction further comprises a selector connected between the first and the second reference potential, wherein the selector can select the first or the second reference potential as reference potential for the at least one transistor.
8. The apparatus for leakage current reduction according to claim 6 , wherein the first reference potential lies in amount between the supply potential and the second reference potential.
9. The apparatus for leakage current reduction according to claim 6 , wherein the at least one transistor is part of an SRAM memory device.
10. The apparatus for leakage current reduction according to claim 6 , wherein the selector is configured to select the second reference potential for a normal operation of the SRAM memory device and select the first reference potential for an energy-saving mode of the SRAM memory device.
11. An apparatus, comprising: a supply potential terminal; a reference potential terminal; a transistor device connected between the supply potential terminal and the reference potential terminal; and a regulating circuit comprising an input for a supply potential signal and an output for a first reference potential signal adjustable in dependence on the supply potential signal, such that a difference between the supply potential signal and the first reference potential signal is maintained at a substantially constant value equal to or higher than a required minimum data retention voltage, wherein the input is connected to the supply potential terminal, and wherein the output is connected to the reference potential terminal.
12. The apparatus according to claim 11 , wherein the apparatus further comprises a selection circuit comprising an input for a selection signal and a switch depending on the selection signal, wherein the switch is configured to apply the first reference potential or a second reference potential to the transistor device as reference potential.
13. The apparatus according to claim 12 , wherein the first reference potential lies in amount between the supply potential and the second reference potential.
14. The apparatus according to claim 12 , wherein the transistor device is part of an SRAM memory device.
15. The apparatus according to claim 11 , wherein the selection circuit is configured to select the second reference potential for a normal operation of the SRAM memory device and select the first reference potential for an energy-saving mode of the SRAM memory device.
16. An SRAM memory device comprising an apparatus for reducing a leakage current of an integrated circuit comprising at least one transistor connected between a supply potential and a first reference potential, comprising: a controller configured to control the first reference potential in dependence on the supply potential, such that a difference between the supply potential and the first reference potential is maintained at a substantially constant value equal to or higher than a required minimum data retention voltage, to retain stored data.
17. An SRAM memory device comprising an apparatus for leakage current reduction for an integrated circuit comprising at least one transistor, comprising: a reference potential regulator comprising a first input for a supply potential, a second input for a reference potential, a terminal for a first reference potential to be regulated in dependence on the supply potential, such that a difference between the supply potential and the first reference potential is maintained at a substantially constant value equal to or higher than a required minimum data retention voltage, to retain stored data, and a terminal for a second reference potential, wherein the at least one transistor is connected between the supply potential and the first reference potential.
18. An SRAM memory device comprising an apparatus, comprising: a supply potential terminal; a reference potential terminal; a transistor device connected between the supply potential terminal and the reference potential terminal; and a regulating circuit comprising an input for a supply potential signal and an output for a reference potential signal adjustable in dependence on the supply potential signal, such that a difference between the supply potential signal and the reference potential signal is maintained at a substantially constant value equal to or higher than a required minimum data retention voltage, to retain stored data, wherein the input is connected to the supply potential terminal, and wherein the output is connected to the reference potential terminal.
19. A method for reducing leakage currents of an integrated circuit comprising at least one transistor, wherein the at least one transistor is connected between a supply potential and a first reference potential, comprising: controlling the first reference potential in dependence on the supply potential, such that a difference between the supply potential and the first reference potential is maintained at a substantially constant value equal to or higher than a required minimum data retention voltage.
20. The method according to claim 19 , further comprising selecting the first reference potential or a second reference potential as reference potential for the at least one transistor, wherein the first reference potential lies in amount between the second reference potential and the supply potential.
21. The method according to claim 19 , wherein the first reference potential is controlled such that a difference of the supply potential and the first reference potential is always higher than 0.5 volt.
22. A computer program comprising a program code for performing the method for reducing leakage currents of an integrated circuit comprising at least one transistor, wherein the at least one transistor is connected between a supply potential and a first reference potential, comprising: controlling the first reference potential in dependence on the supply potential, such that a difference between the supply potential and the first reference potential is maintained at a substantially constant value equal to or higher than a required minimum data retention voltage, when the computer program runs on a computer.
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January 29, 2007
January 13, 2009
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