A method is disclosed for reducing the effects of buckling, also referred to as cracking or wrinkling in multilayer heterostructures. The present method involves forming a planarization layer superjacent a semiconductor substrate. A barrier film having a structural integrity is formed superjacent the planarization layer. A second layer is formed superjacent the barrier film. The substrate is heated sufficiently to cause the planarization layer to expand according to a first thermal coefficient of expansion, the second layer to expand according to a second thermal coefficient of expansion, and the structural integrity of the barrier film to be maintained. This results in the barrier film isolating the planarization layer from the second layer, thereby preventing the planarization layer and the second layer from interacting during the heating step.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device substantially impervious to the effects of buckling, said device comprising: a) a single first planarization layer disposed on a semiconductor substrate, the single first planarization layer having a first reflow temperature and a first thermal coefficient of expansion; b) a barrier film disposed on the single first planarization layer; and c) a single second planarization layer disposed on the barrier film, the single second planarization layer having a second reflow temperature and a second thermal coefficient of expansion, wherein the barrier film does not reflow at the first or second reflow temperatures and retains its structural integrity to isolate the single first planarization layer from the single second planarization layer, thereby preventing the single first planarization layer and the single second planarization layer from interacting, and enabling the single first planarization layer and the single second planarization layer to uniformly reflow.
2. A semiconductor device substantially impervious to the effects of buckling, according to claim 1 , wherein said barrier film comprises at least one of titanium nitride, tantalum nitride, titanium oxide, tantalum oxide, silicon dioxide, silicon nitride and tetraethylorthosilicate (“TEOS”).
3. A semiconductor device substantially impervious to the effects of buckling, according to claim 1 , wherein the single first planarization layer comprises at least one of tungsten, titanium, tantalum, copper, aluminum, single crystal silicon, polycrystalline silicon, amorphous silicon, borophosphosilicate glass (“BPSG”) and tetraethylorthosilicate (“TEOS”).
4. A semiconductor device substantially impervious to the effects of buckling, according to claim 1 , wherein said single second planarization layer comprises at least one of tungsten, titanium, tantalum, copper, aluminum, single crystal silicon, polycrystalline silicon, amorphous silicon, borophosphosilicate glass (“BPSG”) and tetraethylorthosilicate (“TEOS”).
5. A semiconductor device substantially impervious to the effects of buckling, according to claim 1 , wherein the single second planarization layer comprises a metal.
6. A semiconductor device substantially impervious to the effects of buckling, according to claim 1 , wherein the single second planarization layer comprises a refractive metal.
7. A semiconductor device substantially impervious to the effects of buckling, according to claim 1 , wherein the single second planarization layer comprises at least one of boroposphosilicate glass (“BPGS”) and tetraethylorthosilicate (“TEOS”).
8. A planar multilayered semiconductor device comprising: a substrate; a first single flowable layer disposed on the substrate and having a thermal coefficient of expansion; a nitride film disposed on the first layer; and a second single flowable layer disposed on the nitride film, the second single flowable layer having another thermal coefficient of expansion, wherein the nitride film retains its structural integrity at the reflow temperatures of the first single flowable layer and the second single flowable layer, thereby preventing the first single flowable layer and the second single flowable layer from interacting, and enabling the first single flowable layer and the second single flowable layer to uniformly reflow.
9. The planar multilayered semiconductor device according to claim 8 , wherein said nitride film isolates the first single flowable layer from the second single flowable layer, thereby preventing the first single flowable layer and the second single flowable layer from interacting when heated.
10. The planar multilayered semiconductor device according to claim 9 , wherein the first single flowable layer and the second single flowable layer reflow at a temperature of at least 700° C.
11. The planar multilayered semiconductor device according to claim 10 , wherein said nitride film comprises at least one of titanium nitride, tantalum nitride, and silicon nitride.
12. The planar multilayered semiconductor device according to claim 11 , wherein the first single flowable layer comprises at least one of tungsten, titanium, tantalum, copper, aluminum, single crystal silicon, polycrystalline silicon, amorphous silicon, borophosphosilicate glass (“BPSG”) and tetraethylorthosilicate (“TEOS”).
13. The planar multilayered semiconductor device according to claim 12 , wherein the second single flowable layer comprises at least one of tungsten, titanium, tantalum, copper, aluminum, borophosphosilicate glass (“BPSG”) and tetraethylorthosilicate (“TEOS”).
14. The planar multilayered semiconductor device according to claim 12 , wherein the first single flowable layer comprises at least one of single crystal silicon, polycrystalline silicon, amorphous silicon.
15. An apparatus, comprising: a first layer at a temperature of at least 700° C., the first layer being in a reflow state; a second layer at the temperature of at least 700° C., the second layer being in a reflow state; a barrier layer at a temperature of at least 700° C., the barrier layer being disposed between the first and second layers, wherein the barrier layer is not in a reflow state and maintains its structural integrity to isolate the first layer from the second layer.
16. The apparatus of claim, wherein the first layer comprises at least one of tungsten, titanium, tantalum, copper, aluminum, borophosphosilicate glass (“BPSG”) and tetraethylorthosilicate (“TEOS”).
17. The apparatus of claim, wherein the second layer comprises at least one of tungsten, titanium, tantalum, copper, aluminum, borophosphosilicate glass (“BPSG”) and tetraethylorthosilicate (“TEOS”).
18. The apparatus of claim, wherein the barrier layer comprises at least one of titanium nitride, tantalum nitride, titanium oxide, silicon nitride, tantalum oxide, silicon dioxide, borophosphosilicate glass (“BPSG”) and tetraethylorthosilicate (“TEOS”).
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 9, 2004
February 3, 2009
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