A chip structure with a bevel pad row comprises a substrate, a plurality of middle pad rows, and a bevel pad row. The substrate has an active surface including a middle wire bonding area and a corner wire bonding area. The middle wire bonding area is adjacent to a side of the active surface. The corner wire bonding area is adjacent to the side and a end of the middle wire bonding area, and the corner wire bonding area has a bevel edge with an acute incline angle to the side. The middle pad rows are disposed in the middle wire bonding area, and the bevel pad row is disposed along the bevel edge of the corner wire bonding area. The bevel pad row has a plurality of bevel pads, and the quantity of which is greater than that of the middle pad rows in the middle wire bonding area.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A chip structure with a bevel pad row, comprising: a substrate having an active surface, and the active surface comprising: at least a middle wire bonding area adjacent to a side of the active surface; and at least a corner wire bonding area adjacent to the side of the active surface and a end of the middle wire bonding area, wherein the corner wire bonding area has a bevel edge with an acute incline angle to the side of the active surface; a plurality of middle pad rows disposed in the middle wire bonding area and arranged along the side of the active surface; and a bevel pad row disposed in the corner wire bonding area and arranged along the bevel edge, wherein the bevel pad row has a plurality of bevel pads, and a quantity of the bevel pads is greater than a row number of the middle pad rows in the middle wire bonding area.
2. The chip structure with the bevel pad row of claim 1 , wherein the active surface further comprises: a blank area disposed between the middle wire bonding area and the corner wire bonding area.
3. The chip structure with the bevel pad row of claim 1 , further comprising: a plurality of corner pad rows disposed in the corner wire bonding area and arranged along the side of the active surface, wherein the corner pad rows are substantially parallel to the middle pad rows, and the bevel pad row is disposed between the corner pad rows and the middle pad rows.
4. The chip structure with the bevel pad row of claim 3 , wherein each of the corner pad rows comprises a plurality of corner pads, and a first spacing between two adjacent corner pads is greater than or equal to a second spacing between two adjacent bevel pads.
5. The chip structure with the bevel pad row of claim 4 , wherein the middle pad rows comprise a plurality of middle pads, and a third spacing between two adjacent middle pads is shorter than the first spacing.
6. The chip structure with the bevel pad row of claim 1 , wherein the active surface has a corner, the side of the active surface extends to the corner, and the corner wire bonding area is relatively close to the corner than the middle wire bonding area.
7. The chip structure with the bevel pad row of claim 1 , wherein a quantity of the bevel pads in the bevel pad row is determined by an allowable spacing of a bonding wire in a wire bonding process and an acute incline angle.
8. The chip structure with the bevel pad row of claim 2 , wherein the blank area is a triangle.
9. The chip structure with the bevel pad row of claim 2 , wherein the blank area is a trapezoid.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 17, 2006
February 3, 2009
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