Methods for forming leadframe-based semiconductor packages having curvilinear shapes are disclosed. The leadframes may each include one or more curvilinear slots corresponding to curvilinear edges in the finished and singulated semiconductor package. After encapsulation, the integrated circuit packages on the panel may be singulated by cutting the integrated circuits from the leadframe panel into a plurality of individual integrated circuit packages. The slots in the leadframe advantageously allow each leadframe to be singulated using a saw blade making only straight cuts.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of singulating an encapsulated semiconductor package from a panel, the semiconductor package including one or more curvilinear edges and a leadframe including one or more corresponding curvilinear slots, the method consisting essentially of the step of: (a) making a plurality of cuts through the panel along straight lines with a cutting tool.
2. A method of singulating an encapsulated semiconductor package from a panel as recited in claim 1 , said step (a) of making a plurality of cuts through the panel along straight lines including the step of connecting a cut of the plurality of cuts with one or more of the slots during the plurality of straight line cuts.
3. A method of singulating an encapsulated semiconductor package from a panel as recited in claim 1 , said step (a) of making a plurality of cuts through the panel along straight lines including the step of sawing through the panel.
4. A method of singulating an encapsulated semiconductor package from a panel, comprising the steps of: (a) making a first straight line cut along an edge of the semiconductor package, the first straight line cut connecting with a first point along a curvilinear slot defined in the semiconductor package; and (b) making a second straight line cut along an edge of the semiconductor package, the second straight line cut connecting with a second point along the curvilinear slot defined in the semiconductor package, the first straight line cut, the second straight line cut, and an edge of the curvilinear slot defining one or more outer edges of the singulated semiconductor package.
5. A method as recited in step 4 , said steps (a) and (b) comprising the steps of making first and second straight line cuts that are substantially parallel to each other.
6. A method as recited in step 4 , said steps (a) and (b) comprising the steps of making first and second straight line cuts that are substantially orthogonal to each other.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 29, 2005
February 10, 2009
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