Methods of fabricating scalable two-transistor memory devices having metal source/drain regions

1. A method of forming a scalable two-transistor memory (STTM) device, comprising: forming a vertical transistor structure including a storage node on a semiconductor substrate and a tunnel junction structure on the storage node; forming a metal layer on a surface of the substrate adjacent respective opposite sides of the storage node; performing a silicidation process on the substrate including the metal layer on the surface thereof to form spaced apart metal silicide source/drain regions without prior formation of implanted diffusion regions in the substrate adjacent the respective opposite sides of the storage node to define a planar transistor including the storage node of the vertical transistor structure as a floating gate electrode that controls a channel region of the planar transistor; removing unreacted portions of the metal layer from the metal silicide source/drain regions at the surface of the substrate after performing the silicidation process; and then forming a control gate electrode on opposing sidewalls of the tunnel junction structure to define a vertical transistor, wherein the control gate electrode controls a channel region of the vertical transistor.

2. The method of claim 1 , wherein forming the vertical transistor structure comprises: forming the storage node on a surface of the substrate; forming the tunnel junction structure including a tunnel barrier layer and a channel conductive layer on the storage node; and forming sidewall insulating layers on opposing sidewalls of the tunnel junction structure.

3. The method of claim 1 , wherein the metal silicide source/drain regions are formed of, cobalt silicide, nickel silicide, and/or erbium silicide.

4. The method of claim 1 , wherein forming the vertical transistor structure further comprises: forming a data line conductive layer on the tunnel junction structure.

5. The method of claim 4 , wherein forming the tunnel junction structure comprises: alternately forming a plurality of tunnel barrier layers and channel conductive layers on the floating gate electrode.

6. The method of claim 5 , wherein the storage node comprises a polysilicon layer doped with n-type impurity ions, wherein the tunnel barrier layers comprise silicon nitride layers, wherein the channel conductive layers comprise intrinsic polysilicon layers and/or polysilicon layers doped with p-type impurity ions, and wherein the data line conductive layer comprises a polysilicon layer doped with n-type impurity ions and a metal silicide layer.