The present invention provides a process for manufacturing a semiconductor device that can be incorporated into an integrated circuit. The method includes, forming a first doped layer of isotopically enriched silicon over a foundational substrate, forming a second layer of an isotopically enriched semiconductor material silicon over the first doped layer, and constructing active devices on the second layer. The device includes a first doped layer of an isotopically enriched semiconductor material and a second layer of an isotopically enriched semiconductor material located over the first doped layer, and active devices located on the second layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A process for manufacturing a semiconductor device, comprising: forming a first doped layer of an isotopically enriched semiconductor material over a foundational substrate, said first doped layer having a first dopant concentration; forming a second layer of isotopically enriched semiconductor material over and in contact with said first doped layer, said second layer having a second different dopant concentration; and constructing active devices on said second layer.
2. The process as recited in claim 1 , further including removing said foundational substrate.
3. The process as recited in claim 1 , wherein said first doped layer and said second layer are isotopically enriched with silicon 28 ( 28 Si).
4. The process as recited in claim 3 , wherein said 28 Si accounts for greater than about 93% of silicon present in each of said first doped layer and said second layer.
5. The process as recited in claim 1 wherein said first doped layer and said second layer are epitaxially deposited over said foundational substrate, and said first doped layer is doped during said epitaxial deposition.
6. The process as recited in claim 5 wherein said second layer is also doped.
7. The process as recited in claim 1 wherein forming said first and second doped layers includes forming said first doped layer to a thickness of about 40 microns and forming said second layer to a thickness of about 10 microns.
8. A process, for manufacturing a semiconductor device, comprising: forming a first doped layer of an isotopically enriched semiconductor material over a foundational substrate, said first doped layer having a dopant concentration ranging from about 1E18 to about 1E20 atoms/cm 3 ; forming a second doped layer of isotopically enriched semiconductor material over and in contact with said first doped layer wherein said second layer is doped to a concentration ranging from about 1E13 to about 2E15 atoms/cm 3 ; and constructing active devices on said second layer.
9. A semiconductor device, comprising: a first doped layer of an isotopically enriched semiconductor material, said first doped layer having a first dopant concentration; a second layer of isotopically enriched semiconductor material located over and in contact with said first doped layer, said second layer having a second different dopant concentration; and active devices located on said second layer.
10. The semiconductor device as recited in claim 9 wherein said first doped layer is a support layer that serves as an electrical back contact for said semiconductor device.
11. The semiconductor device as recited in claim 10 wherein said first doped layer and said second layer are isotopically enriched with silicon 28 ( 28 Si).
12. The semiconductor device as recited in claim 10 wherein said 28 Si accounts for greater than about 93% of silicon present in each of said first doped layer and said second layer.
13. The semiconductor device as recited in claim 9 wherein a thickness of said first doped layer is about 40 microns and a thickness of said second layer is about 10 microns.
14. A semiconductor device comprising: a first doped layer of an isotopically enriched semiconductor material, said first doped layer having a dopant concentration ranging from about 1E18 to about 1E20 atoms/cm 3 ; a second doped layer of isotopically enriched semiconductor material located over and in contact with said first doped layer, said second having a dopant concentration ranging from about 1E13 to about 2E15 atoms/cm 3 ; and active devices located on said second layer.
15. The semiconductor device as recited in claim 14 wherein said first and second doped layers are doped with a p-type dopant or an n-type of dopant.
16. An integrated circuit comprising: a first doped layer of isotopically enriched silicon, said first doped layer having a first dopant concentration; a second doped layer of isotopically enriched silicon located over and in contact with said first doped layer, said second doped layer having a second different dopant concentration; and active devices located on or within said second doped layer; dielectric layers located over said active devices; and interconnects located in dielectric layers and interconnecting said active devices to form an operative integrated circuit.
17. The integrated circuit as recited in claim 16 wherein said first doped layer is a base layer and an electrical back contact for said integrated circuit.
18. The integrated circuit as recited in claim 16 wherein said first and second doped layers are isotopically enriched silicon with silicon 28 ( 28 Si).
19. The integrated circuit as recited in claim 16 wherein said first doped layer is doped to a dopant concentration of about 1E19 atoms/cm 3 .
20. The integrated circuit as recited in claim 16 wherein a thickness of said first doped layer is about 40 microns and a thickness of said second doped layer is about 10 microns.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 23, 2004
February 24, 2009
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.