Patentable/Patents/US-7498228
US-7498228

Method for fabricating SONOS a memory

PublishedMarch 3, 2009
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A method for fabricating a SONOS memory is disclosed. First, a semiconductor substrate is provided and a SONOS memory cell is formed on said semiconductor substrate. A passivation layer is deposited on the SONOS memory cell and a contact pad is formed on the passivation layer. Subsequently, an ultraviolet treatment is performed and an annealing process is conducted thereafter.

Patent Claims
17 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method for fabricating a SONOS memory, comprising: providing a semiconductor substrate; forming a SONOS memory cell on the semiconductor substrate; depositing a passivation layer on the SONOS memory cell; forming a contact pad in the opening of the passivation layer; performing a first ultraviolet treatment; and performing a first annealing process after the first ultraviolet treatment.

2

2. The method for fabricating a SONOS memory of claim 1 further comprising: forming a first silicon oxide layer on the semiconductor substrate; forming a silicon nitride layer on the first silicon oxide layer; forming a second silicon oxide layer on the silicon nitride layer; forming a polysilicon layer on the second silicon oxide layer; performing a pattern transfer process to form a stacked gate on the semiconductor substrate; and performing an ion implantation process to form a source/drain region in the semiconductor substrate beside the two sides of the stacked gate.

3

3. The method for fabricating a SONOS memory of claim 1 further comprising: forming an oxide-nitride-oxide (ONO) structure on the semiconductor substrate; performing an ion implantation process to form a source/drain region in the semiconductor substrate beside the two sides of the ONO structure; forming a polysilicon layer on the ONO structure; and performing a pattern transfer process to form a stacked gate on the semiconductor substrate.

4

4. The method for fabricating a SONOS memory of claim 1 further comprising forming an inter-layer dielectric on the SONOS memory cell after forming the passivation layer.

5

5. The method for fabricating a SONOS memory of claim 4 further comprising forming a plurality of contact plugs in the inter-layer dielectric.

6

6. The method for fabricating a SONOS memory of claim 5 further comprising performing a metal interconnection process for forming a plurality of inter-metal dielectric and metal interconnects on the inter-layer dielectric.

7

7. The method for fabricating a SONOS memory of claim 1 , wherein the step of forming the contact pad further comprises: forming a top patterned metal layer; forming the passivation layer on the top patterned metal layer; forming a patterned photoresist on the passivation layer; and performing an etching process to form an opening in the passivation layer for exposing the top patterned metal layer.

8

8. The method for fabricating a SONOS memory of claim 7 , wherein the top patterned metal layer comprises copper, aluminum or alloy thereof.

9

9. The method for fabricating a SONOS memory of claim 1 , wherein the power of the first ultraviolet treatment is between 20 mW to 40 mW.

10

10. The method for fabricating a SONOS memory of claim 1 , wherein the wavelength of the first ultraviolet treatment is about 250 nm.

11

11. The method for fabricating a SONOS memory of claim 1 further comprising performing a second ultraviolet treatment after forming the passivation layer.

12

12. The method for fabricating a SONOS memory of claim 11 , wherein the power of the second ultraviolet treatment is between 20 mW to 40 mW.

13

13. The method for fabricating a SONOS memory of claim 11 , wherein the wavelength of the second ultraviolet treatment is about 250 nm.

14

14. The method for fabricating a SONOS memory of claim 1 , wherein the temperature of the first annealing process is between 250° C. to 410° C.

15

15. The method for fabricating a SONOS memory of claim 1 , wherein the duration of the first annealing process is about 2 hours.

16

16. The method for fabricating a SONOS memory of claim 1 further comprising performing a second annealing process after performing the first annealing process.

17

17. The method for fabricating a SONOS memory of claim 1 further comprising performing a second ultraviolet treatment and a second annealing process after performing the first annealing process.

Classification Codes (CPC)

Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.

Patent Metadata

Filing Date

July 9, 2007

Publication Date

March 3, 2009

Want to explore more patents?

Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.

Citation & reuse

Analysis on this page is generated by Patentable — an AI-powered patent intelligence platform. AI-generated summaries, explanations, and analysis may be reused with attribution and a visible link back to the canonical URL below. Patent abstracts and claims are USPTO public domain.

Cite as: Patentable. “Method for fabricating SONOS a memory” (US-7498228). https://patentable.app/patents/US-7498228

© 2026 Patentable. All rights reserved.

Patentable is a research and drafting-assistant tool, not a law firm, and does not provide legal advice. Documents we generate are drafts for review by a licensed patent attorney.