A semiconductor memory apparatus includes a bank that includes a core block where a memory cell array is disposed and a control block to drive the memory cell array, a ground power supply pad that is supplied with a ground power through a ground line, a switch that connects the ground line and the core block, and a block control unit that controls an on/off operation of the switch.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor memory apparatus comprising: a bank that includes a core block having a memory cell array, bit line sense amplifier array, a sub-hole and a sub word line driver array and a control block for driving the memory cell array; a ground power supply pad configured to receive a ground power through a ground line; a switch configured to connect the ground line and ground terminals the core block; and a block control unit configured to control an on/off operation of the switch, wherein the ground terminals include a first ground terminal being ground terminals of the bit line sense amplifier array and the sub-hole, and a second ground terminal being a ground terminal of the sub word line driver array.
2. The semiconductor memory apparatus of claim 1 , wherein the bank further includes: a row control block configured to drive a row address path of the core block; a column control block configured to drive a column address path of the core block; and a bank internal control block configured to control the row control block and the column control block according to a bank selection command.
3. The semiconductor memory apparatus of claim 2 , wherein the row control block, the column control block, and the bank internal control block are connected in common to the ground power supply pad.
4. The semiconductor memory apparatus of claim 1 , wherein the block control unit includes: an input unit configured to receive a clock enable signal and a self refresh signal and produce an output signal based thereon; and a driver configured to output a block control signal controlling the switch in response to the output signal of the input unit.
5. The semiconductor memory apparatus of claim 4 , wherein the input unit is composed of a NOR gate configured to receive the clock enable signal and the self refresh signal as input.
6. The semiconductor memory apparatus of claim 4 , wherein the driver is composed of an inverter configured to receive the output signal of the input unit as input.
7. The semiconductor memory apparatus of claim 4 , wherein the driver is composed of a level shifter configured to receive the output signal of the input unit and convert a level of the output signal of the input unit.
8. The semiconductor memory apparatus of claim 1 , wherein the switch is composed of a NMOS transistor.
9. The semiconductor memory apparatus of claim 1 , wherein the core block includes: the memory cell array where a plurality of memory cells are disposed; the bit line sense amplifier array where a plurality of sense amplifiers, each sensing data of each of the memory cells, are disposed; a sub word line driver array configured to drive word lines of the memory cells; and a sub hole where a relay is disposed to relay a bit line dividing signal and a bit line equalizing signal.
10. The semiconductor memory apparatus of claim 9 , wherein the core block further includes: a first core ground line configured to supply the ground power to the bit line sense amplifier array and the sub hole; and a second core ground line configured to supply the ground power to the sub word line driver array.
11. The semiconductor memory apparatus of claim 10 , wherein the first ground line and the second ground line branch from the switch.
12. The semiconductor memory apparatus of claim 1 , wherein the ground power supply pad is disposed outside the bank.
13. The semiconductor memory apparatus of claim 1 , wherein the block control unit is disposed outside the bank.
14. A semiconductor memory apparatus comprising: a bank that includes a core block where a memory cell array is disposed and a control block to drive the memory cell array; a ground power supply pad configured to receive a ground power supply through a ground line; a switch configured to connect the ground power supply pad and ground terminals of the control block; and a block control unit configured to control an on/off operation of the switch, wherein the control block includes: a row control block configured to control a row address path of the core block; a column control block configured to control a column address path of the core block; and a bank internal control block configured to control the row control block and the column control block according to a bank selection command, wherein the row control block, the column control block and the bank internal control block are connected in common to the ground power supply pad through the switch.
15. The semiconductor memory apparatus of claim 14 , wherein the block control unit includes: an input unit configured to receive a clock enable signal and a self refresh signal and produce an output signal based thereon; and a driver that outputs a block control signal controlling the switch in response to the output signal of the input unit.
16. The semiconductor memory apparatus of claim 14 , wherein the switch is composed of an NMOS transistor.
17. The semiconductor memory apparatus of claim 14 , further comprising: a first core ground line that connects the ground line and the core block; and a second core ground line that connects the ground line and the core block.
18. The semiconductor memory apparatus of claim 17 , wherein the core block includes: the memory cell array where a plurality of memory cells are disposed; a bit line sense amplifier array where plurality of sense amplifiers, each sensing data of each of the memory cells, are disposed; a sub word line driver array configured to drive word lines of the memory cells; and a sub hole where a relay is disposed to relay a bit line dividing signal and a bit line equalizing signal.
19. The semiconductor memory apparatus of claim 18 , wherein, in the core block, the bit line sense amplifier array and the sub hole are connected to the first core ground line, and the sub word line driver is connected to the second core ground line.
20. The semiconductor memory apparatus of claim 19 , wherein the ground power supply pad and the block control unit are disposed outside the bank.
21. A semiconductor memory apparatus comprising: a bank that includes a core block where a memory cell array is disposed and a control block to drive the memory cell array; a ground power supply pad configured to receive a ground power supply through a ground line; a switch configured to connect the ground power supply pad and each ground terminal of the bank; and a block control unit configured to control an on/off operation of the switch; wherein the core block includes the memory cell array where a plurality of memory cells are disposed; a bit line sense amplifier array where plurality of sense amplifiers, each sensing data of each of the memory cells, are disposed; a sub word line driver array configured to drive word lines of the memory cells; and a sub hole where a relay is disposed to relay a bit line dividing signal and a bit line equalizing signal, wherein, in the core block, the bit line sense amplifier array and the sub hole are connected to a first core ground line, and the sub word line driver array is connected to a second core ground line.
22. The semiconductor memory apparatus of claim 21 , wherein the bank further includes: a row control block configured to drive a row address path of the core block; a column control block configured to drive a column address path of the core block; and a bank control unit configured to control the row control block and the column control block according to a bank selection command.
23. The semiconductor memory apparatus of claim 22 , wherein the ground terminals of the row control block, the column control block, and the bank internal control block are connected in common to the switch.
24. The semiconductor memory apparatus of claim 22 , wherein the bank control unit includes: a delay configured to delay a row active signal to produce an output signal; an input unit configured to receive the row active signal and the output signal of the delay and to produce an output based thereon; and a driver configured to output a bank control signal controlling the switch in response to the output signal of the input unit.
25. The semiconductor memory apparatus of claim 21 , wherein the switch is composed of an NMOS transistor.
26. The semiconductor memory apparatus of claim 22 , wherein the ground power supply pad and the bank control unit are disposed outside the bank.
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December 12, 2006
March 3, 2009
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