A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A phase-change cell memory device, comprising: a plurality of phase-change memory cells each including a volume of material programmable between amorphous and crystalline states; an address circuit for selecting at least one of the memory cells; a write driver for generating a reset sloped pulse current to program a memory cell selected by the address circuit into the amorphous state, and generating a set sloped pulse current to program the memory cell selected by the address circuit into the crystalline state; and a write driver control circuit coupled to the address circuit, the write driver control circuit for varying at least one of a pulse width and pulse slope of at least one of the reset and set sloped pulse currents according to a load between the write driver and the memory cell selected by the address circuit, wherein the write driver control circuit varies a pulse width of at least one of the reset and set slope pulse currents, and wherein the pulse width of the reset sloped pulse current is constant, and wherein the write driver control circuit decreases a pulse width of the set sloped pulse current with an increase in load between the write driver and the memory cells selected by the address circuit.
2. A phase-change cell memory device, comprising: a plurality of phase-change memory cells each including a volume of material programmable between amorphous and crystalline states; an address circuit for selecting at least one of the memory cells; a write driver for generating a reset sloped pulse current to program a memory cell selected by the address circuit into the amorphous state, and generating a set sloped pulse current to program the memory cell selected by the address circuit into the crystalline state; and a write driver control circuit coupled to the address circuit, the write driver control circuit for varying at least one of a pulse width and pulse slope of at least one of the reset and set sloped pulse currents according to a load between the write driver and the memory cell selected by the address circuit, wherein the write driver control circuit varies a pulse width of at least one of the reset and set slope pulse currents, and wherein the pulse width of the set sloped pulse current is constant, and wherein the write driver control circuit decreases a pulse width of the reset sloped pulse current with an increase in load between the write driver and the memory cells selected by the address circuit.
3. A phase-change cell memory device, comprising: a plurality of phase-change memory cells each including a volume of material programmable between amorphous and crystalline states; an address circuit for selecting at least one of the memory cells; a write driver for generating a reset sloped pulse current to program a memory cell selected by the address circuit into the amorphous state, and generating a set sloped pulse current to program the memory cell selected by the address circuit into the crystalline state; and a write driver control circuit coupled to the address circuit, the write driver control circuit for varying at least one of a pulse width and pulse slope of at least one of the reset and set sloped pulse currents according to a load between the write driver and the memory cell selected by the address circuit, wherein the write driver control circuit varies a pulse width of at least one of the reset and set slope pulse currents, and wherein the pulse width of the reset sloped pulse current is constant, and wherein the write driver control circuit increases a pulse width of the set sloped pulse current with an increase in load between the write driver and the memory cells selected by the address circuit.
4. A phase-change cell memory device, comprising: a plurality of phase-change memory cells each including a volume of material programmable between amorphous and crystalline states; an address circuit for selecting at least one of the memory cells; a write driver for generating a reset sloped pulse current to program a memory cell selected by the address circuit into the amorphous state, and generating a set sloped pulse current to program the memory cell selected by the address circuit into the crystalline state; and a write driver control circuit coupled to the address circuit, the write driver control circuit for varying at least one of a pulse width and pulse slope of at least one of the reset and set sloped pulse currents according to a load between the write driver and the memory cell selected by the address circuit, wherein the write driver control circuit varies a pulse width of at least one of the reset and set slope pulse currents, wherein the pulse width of the set sloped pulse current is constant, and wherein the write driver control circuit increases a pulse width of the reset sloped pulse current with an increase in load between the write driver and the memory cells selected by the address circuit.
5. A phase-change cell memory device, comprising: a plurality of phase-change memory cells each including a volume of material programmable between amorphous and crystalline states; an address circuit for selecting at least one of the memory cells; a write driver for generating a reset sloped pulse current to program a memory cell selected by the address circuit into the amorphous state, and generating a set sloped pulse current to program the memory cell selected by the address circuit into the crystalline state; and a write driver control circuit coupled to the address circuit, the write driver control circuit for varying at least one of a pulse width and pulse slope of at least one of the reset and set sloped pulse currents according to a load between the write driver and the memory cell selected by the address circuit, wherein the write driver control circuit varies a pulse width of at least one of the reset and set slope pulse currents, wherein the write driver control circuit increases a pulse width of the set and reset sloped pulse currents with an increase in load between the write driver and the memory cells selected by the address circuit.
6. A phase-change cell memory device, comprising: a plurality of phase-change memory cells each including a volume of material programmable between amorphous and crystalline states; an address circuit for selecting at least one of the memory cells; a write driver for generating a reset sloped pulse current to program a memory cell selected by the address circuit into the amorphous state, and generating a set sloped pulse current to program the memory cell selected by the address circuit into the crystalline state; and a write driver control circuit coupled to the address circuit, the write driver control circuit for varying at least one of a pulse width and pulse slope of at least one of the reset and set sloped pulse currents according to a load between the write driver and the memory cell selected by the address circuit, wherein the write driver control circuit varies a pulse slope of at least one of the reset and set slope pulse currents, and wherein the pulse slope of the reset sloped pulse current is constant, and wherein the write driver control circuit decreases a pulse slope of the set sloped pulse current with an increase in load between the write driver and the memory cells selected by the address circuit.
7. A phase-change cell memory device, comprising: a plurality of phase-change memory cells each including a volume of material programmable between amorphous and crystalline states; an address circuit for selecting at least one of the memory cells; a write driver for generating a reset sloped pulse current to program a memory cell selected by the address circuit into the amorphous state, and generating a set sloped pulse current to program the memory cell selected by the address circuit into the crystalline state; and a write driver control circuit coupled to the address circuit, the write driver control circuit for varying at least one of a pulse width and pulse slope of at least one of the reset and set sloped pulse currents according to a load between the write driver and the memory cell selected by the address circuit, wherein the write driver control circuit varies a pulse slope of at least one of the reset and set slope pulse currents, and wherein the pulse slope of the set sloped pulse current is constant, and wherein the write driver control circuit decreases a pulse slope of the reset sloped pulse current with an increase in load between the write driver and the memory cells selected by the address circuit.
8. A phase-change cell memory device, comprising: a plurality of phase-change memory cells each including a volume of material programmable between amorphous and crystalline states; an address circuit for selecting at least one of the memory cells; a write driver for generating a reset sloped pulse current to program a memory cell selected by the address circuit into the amorphous state, and generating a set sloped pulse current to program the memory cell selected by the address circuit into the crystalline state; and a write driver control circuit coupled to the address circuit, the write driver control circuit for varying at least one of a pulse width and pulse slope of at least one of the reset and set sloped pulse currents according to a load between the write driver and the memory cell selected by the address circuit, wherein the write driver control circuit varies a pulse slope of at least one of the reset and set slope pulse currents, and wherein the pulse slope of the reset sloped pulse current is constant, and wherein the write driver control circuit increases a pulse slope of the set sloped pulse current with an increase in load between the write driver and the memory cells selected by the address circuit.
9. A phase-change cell memory device, comprising: a plurality of phase-change memory cells each including a volume of material programmable between amorphous and crystalline states; an address circuit for selecting at least one of the memory cells; a write driver for generating a reset sloped pulse current to program a memory cell selected by the address circuit into the amorphous state, and generating a set sloped pulse current to program the memory cell selected by the address circuit into the crystalline state; and a write driver control circuit coupled to the address circuit, the write driver control circuit for varying at least one of a pulse width and pulse slope of at least one of the reset and set sloped pulse currents according to a load between the write driver and the memory cell selected by the address circuit, wherein the write driver control circuit varies a pulse slope of at least one of the reset and set slope pulse currents, and wherein the pulse slope of the set sloped pulse current is constant, and wherein the write driver control circuit increases a pulse slope of the reset sloped pulse current with an increase in load between the write driver and the memory cells selected by the address circuit.
10. A phase-change cell memory device, comprising: a plurality of phase-change memory cells each including a volume of material programmable between amorphous and crystalline states; an address circuit for selecting at least one of the memory cells; a write driver for generating a reset sloped pulse current to program a memory cell selected by the address circuit into the amorphous state, and generating a set sloped pulse current to program the memory cell selected by the address circuit into the crystalline state; and a write driver control circuit coupled to the address circuit, the write driver control circuit for varying at least one of a pulse width and pulse slope of at least one of the reset and set sloped pulse currents according to a load between the write driver and the memory cell selected by the address circuit, wherein the write driver control circuit varies a pulse slope of at least one of the reset and set slope pulse currents, and wherein the write driver control circuit increases a pulse slope of the set and reset sloped pulse currents with an increase in load between the write driver and the memory cells selected by the address circuit.
11. A phase-change cell memory device, comprising: a plurality of phase-change memory cells each including a volume of material programmable between amorphous and crystalline states; an address circuit for selecting at least one of the memory cells; a write driver for generating a reset sloped pulse current to program a memory cell selected by the address circuit into the amorphous state, and generating a set sloped pulse current to program the memory cell selected by the address circuit into the crystalline state; a write driver control circuit coupled to the address circuit, the write driver control circuit for varying at least one of a pulse width and pulse slope of at least one of the reset and set sloped pulse currents according to a load between the write driver and the memory cell selected by the address circuit; and a sloped pulse generator which generates stepped voltage signals, wherein a pulse slope of the set and reset sloped pulse currents corresponds to a speed at which the slope pulse generator generates the stepped voltage signals.
12. A phase-change cell memory device, comprising: a plurality of memory cell blocks each including a plurality of phase-change memory cells, each of the phase-change memory cells having a volume of material programmable between amorphous and crystalline states; an address circuit for selecting each of the memory cell blocks; a write driver for selectively generating a reset sloped pulse current to program memory cells of a memory cell block selected by the address circuit into the amorphous set state, and a set sloped pulse current to program memory cells of the memory cell block selected by the address circuit into the crystalline state; and a write driver control circuit for varying at least one of a pulse width and a pulse slope of at least one of the reset and set sloped pulse currents according to the memory cell block selected by the address circuit.
13. The device of claim 12 , wherein the write driver control circuit varies a pulse width of at least one of the set and reset sloped pulse currents according to a load between the write driver and the memory cell block selected by the address circuit.
14. The device of claim 12 , wherein the write driver control circuit varies a pulse slope of at least one of the set and reset sloped pulse currents according to the load between the write driver and the memory cell block selected by the address circuit.
15. The device of claim 12 , further comprising a sloped pulse generator which generates stepped voltage signals, wherein a pulse slope of the set and reset sloped pulse currents corresponds to a speed at which the slope pulse generator generates the stepped voltage signals.
16. A phase-change cell memory device, comprising: a phase-change memory cell array including a plurality of word lines and bit lines and a plurality of phase-change cells at respective intersection regions of the word lines and bit lines, the memory cell array being defined by a plurality of memory blocks each including at least one word line, and each of the phase-change memory cells including a volume of material programmable between amorphous and crystalline states; an address decoder for decoding an input row address to select a word line of each memory block and to select one of the memory blocks; a bit line selection circuit for selecting at least one bit line according to an input column address; a write driver coupled to the bit line selection circuit, for selectively generating a reset sloped pulse current to program a memory cell at the intersection of a selected bit line and word line within the selected memory cell block into the amorphous set state, and a set sloped pulse current to program a memory cell at the intersection of the selected bit line and word line within the selected memory cell block into the crystalline state; and a write driver control circuit for varying at least one of a pulse width and a pulse slope of at least one of the reset and set sloped pulse currents according to the memory cell block selected by the address decoder.
17. A method of programming a phase-change memory device having a plurality of phase-change memory cells, the plurality of phase-change memory cells each including a volume of material programmable between amorphous and crystalline states, the method comprising: using a write driver to selectively generate a reset sloped pulse current to program the memory cells selected by an address circuit into the amorphous set state, and a set sloped pulse current to program the memory cells selected by the address circuit into the crystalline state; and varying at least one of a pulse width and a pulse slope of at least one of the reset and set sloped pulse currents according to a load between the writer driver and the memory cells being programmed, wherein the pulse width of the reset sloped pulse current is constant, and wherein a pulse width of the set sloped pulse current is increased or decreased with an increase in load between the writer driver and the memory cells selected by the address circuit.
18. A phase-change cell memory device, comprising: a plurality of phase-change memory cells each including a volume of material programmable between amorphous and crystalline states; an address circuit for selecting at least one of the memory cells; a write driver for generating a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and generating a set pulse current to program the memory cell selected by the address circuit into the crystalline state; and a write driver control circuit coupled to the address circuit, the write driver control circuit for varying at least one of the reset and set pulse currents according to a load of word line of the memory cell selected by the address circuit, wherein the write driver control circuit constantly preserves the reset pulse current and varies any one of a pulse width, a pulse level and the number of pulses in the set pulse current.
19. A phase-change cell memory device, comprising: a plurality of phase-change memory cells each including a volume of material programmable between amorphous and crystalline states; an address circuit for selecting at least one of the memory cells; a write driver for generating a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and generating a set pulse current to program the memory cell selected by the address circuit into the crystalline state; and a write driver control circuit coupled to the address circuit, the write driver control circuit for varying at least one of the reset and set pulse currents according to a load of word line of the memory cell selected by the address circuit, wherein the write driver control circuit constantly preserves the reset pulse current, and varies any one of a slope pulse width and a slope pulse level of the set pulse current.
20. A phase-change cell memory device, comprising: a plurality of phase-change memory cells each including a volume of material programmable between amorphous and crystalline states; an address circuit for selecting at least one of the memory cells; a write driver for generating a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and generating a set pulse current to program the memory cell selected by the address circuit into the crystalline state; and a write driver control circuit coupled to the address circuit, the write driver control circuit for varying at least one of the reset and set pulse currents according to a load of word line of the memory cell selected by the address circuit wherein the write driver control circuit constantly preserves the set pulse current, and varies any one of a pulse width, a pulse level and the number of pulses in the reset pulse current.
21. A phase-change cell memory device, comprising: a plurality of phase-change memory cells each including a volume of material programmable between amorphous and crystalline states; an address circuit for selecting at least one of the memory cells; a write driver for generating a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and generating a set pulse current to program the memory cell selected by the address circuit into the crystalline state; and a write driver control circuit coupled to the address circuit, the write driver control circuit for varying at least one of the reset and set pulse currents according to a load of word line of the memory cell selected by the address circuit wherein the write driver control circuit constantly preserves the set pulse current, and varies any one of a slope pulse width and a slope pulse level of the reset pulse current.
22. The device of claim 18 , wherein the pulse width or pulse number of the reset pulse current is constant, and the write driver control circuit reduces the pulse width or pulse number of the set pulse current according to a word line load increase of the memory cells coupled to the same word line.
23. The device of claim 18 , wherein a unit memory cell of the phase-change memory cells includes one variable resistance formed of phase-change material, and a diode connected between the variable resistance and a word line.
24. A phase-change cell memory device, comprising: a plurality of memory cell blocks each including a plurality of phase-change memory cells, each of the phase-change memory cells having a volume of material programmable between amorphous and crystalline states; an address circuit for selecting each of the memory cell blocks; a write driver for selectively generating a reset pulse current to program memory cells of a memory cell block selected by the address circuit into the amorphous set state, and a set pulse current to program memory cells of the memory cell block selected by the address circuit into the crystalline state; and a write driver control circuit for varying a pulse width, pulse level, pulse number or pulse slope of at least one of the reset and set pulse currents according to a load of word line of the memory cell block selected by the address circuit.
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August 11, 2006
March 10, 2009
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