A program method of a flash memory device having first and-second bitlines connected with a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The program method includes programming memory cells, connected to a selected row and first or second bitlines, with multi-bit data; and reprogramming programmed memory cells connected to a row disposed directly below the selected row and the first bitlines or the second bitlines, whereby increasing a read margin between adjacent states reduced due to high temperature stress (HTS).
Legal claims defining the scope of protection, as filed with the USPTO.
1. A program method of a flash memory device having first and second bitlines connected with a plurality of memory cells for storing multi-bit data indicating one of a plurality of states, the program method comprising: (a) programming memory cells, connected to a selected row and first or second bitlines, with multi-bit data; and (b) reprogramming programmed memory cells connected to a row disposed directly below the selected row and the first bitlines or the second bitlines, whereby increasing a read margin between adjacent states of said plurality of states reduced due to high temperature stress (HTS).
2. The program method as recited in claim 1 , wherein the step of reprogramming further comprises: detecting memory cells arranged within a predetermined threshold voltage region among the memory cells of the respective states wherein the predetermined threshold region of the respective states is selected by both one of a first verify voltage and a read voltage and a second verify voltage, the first verify voltage being higher than the second verify voltage and lower than the read voltage; and programming the detected memory cells to have a threshold voltage equivalent to or higher than the second verify voltage corresponding to the respective states.
3. The program method as recited in claim 2 , wherein the first verify voltage corresponding to the respective states is used to determine whether the selected memory cells are programmed with multi-bit data.
4. The program method as recited in claim 2 , wherein when the detected memory cells are programmed to have a threshold voltage equivalent to or higher than the second verify voltage corresponding to the respective states, a program voltage is applied to a selected wordline by a predetermined increment according to the respective states.
5. The program method as recited in claim 2 , wherein when the detected memory cells are programmed to have a threshold voltage equivalent to or higher than the second verify voltage corresponding to the respective states, a program voltage is applied to a selected wordline by a constant amount regardless of the respective state.
6. The program method as recited in claim 4 , wherein the program voltage is repeatedly applied to the selected wordline until the threshold voltage is equivalent to or higher than the second verify voltage.
7. The program method as recited in claim 1 , wherein the selected row comprises at least two pages each including an LSB page and an MSB page wherein two page data are stored in the memory cells connected with the bitlines.
8. The program method as recited in claim 1 , wherein the multi-bit data includes LSB page data and MSB page data wherein one page data is stored in the memory cells connected with the bitlines.
9. A program method of a flash memory device having first and second bitlines connected with a plurality of memory cells for storing multi-bit data indicating one of a plurality of states, the program method comprising: programming memory cells, connected to a selected row and the first bitline, with multi-bit data; and reprogramming programmed memory cells connected to a row disposed directly below the selected row and the first bitlines, wherein said reprogramming increases a read margin between adjacent states of said plurality of states where a threshold voltage associated with said memory cells was decreased due to high temperature stress (HTS).
10. The program method as recited in claim 9 , further comprising: programming memory cells, connected to the selected row and the second bitlines, with multi-bit data; and reprogramming programmed memory cells connected to a row disposed directly below the selected row and the second bitlines, wherein said reprogramming increases a read margin between adjacent states of said plurality of states where a threshold voltage associated with said memory cells was decreased due to high temperature stress (HTS).
11. A program method of a flash memory device having first and second bitlines connected with a plurality of memory cells for storing multi-bit data indicating one of a plurality of states, the program method comprising: programming memory cells, connected to a selected wordline and the second bitlines, with multi-bit data; and reprogramming programmed memory cells connected to a row disposed directly below the selected row and the first bitlines, wherein said reprogramming increases a read margin between adjacent states of said plurality of states where a threshold voltage associated with said memory cells was decreased due to high temperature stress (HTS).
12. The program method as recited in claim 11 , wherein the step of reprogramming further comprises: detecting memory cells arranged within a predetermined region of a threshold voltage region among the memory cells of the respective states distribution where programmed memory cells of the respective states are distributed, wherein the predetermined threshold region of the respective states is selected by both one of a first verify voltage and a read voltage and a second verify voltage, the first verify voltage being higher than the second verify voltage and lower than the read voltage; and programming the detected memory cells to have a threshold voltage equivalent to or higher than the second verify voltage corresponding to the respective states.
13. The program method as recited in claim 12 , wherein the first verify voltage corresponding to the respective state is used to determine whether the selected memory cells are programmed with multi-bit data.
14. The program method as recited in claim 12 , wherein if the detected memory cells are programmed to have a threshold voltage equivalent to or higher than the second verify voltage corresponding to the respective states, a program voltage is applied to a selected wordline by a predetermined increment according to the respective states.
15. The program method as recited in claim 12 , wherein when the detected memory cells are programmed to have a threshold voltage equivalent to or higher than the second verify voltage corresponding to the respective states, a program voltage is applied to a selected wordline by a constant amount regardless of the respective state.
16. The program method as recited in claim 14 , wherein the program voltage is repeatedly applied to a selected wordline until the threshold voltage is equivalent to or higher than the second verify voltage.
17. The program method as recited in claim 11 , further comprising: reprogramming programmed memory cells connected to a row disposed directly below the selected row and the second bitlines such that said reprogramming increases a read margin between adjacent states of said plurality of states where a threshold voltage associated with said memory cells was decreased due to high temperature stress (HTS).
18. The program method as recited in claim 17 , wherein the step of reprogramming programmed memory cells further comprises: detecting the programmed memory cells arranged within a predetermined threshold voltage region among the memory cells of the respective states wherein the predetermined region of the respective states is selected from both one of a first verify voltage and a read voltage and a second verify voltage, the first verify voltage being higher than the second verify voltage and lower than the read voltage; and programming the detected memory cells to have a threshold voltage equivalent to or higher than the second verify voltage corresponding to the respective states.
19. The program method as recited in claim 18 , wherein the first verify voltage corresponding to the respective state is used to determine whether the selected memory cells are programmed with multi-bit data.
20. The program method as recited in claim 18 , wherein when the detected memory cells are programmed to have a threshold voltage equivalent to or higher than the second verify voltage corresponding to the respective states, a program voltage is applied to a selected wordline by a predetermined increment according to the respective states.
21. The program method as recited in claim 18 , wherein when the detected memory cells are programmed to have a threshold voltage equivalent to or higher than the second verify voltage corresponding to the respective states, a program voltage is applied to a selected wordline by a constant amount regardless of the respective state.
22. The program method as recited in claim 20 , wherein the program voltage is repeatedly applied to a selected wordline until the threshold voltage is equivalent to or higher than the second verify voltage.
23. The program method as recited in claim 11 , further comprising: programming memory cells, connected to the selected row and the first bitlines, with multi-bit data corresponding to a memory state when the memory cells connected to the selected row and the first bitlines are selected.
24. The program method as recited in claim 11 , wherein the selected row comprises at least two pages each including an LSB page and an MSB page wherein two page data are stored in the memory cells connected with the bitlines.
25. The program method as recited in claim 11 , wherein the multi-bit data includes LSB page data and MSB page data wherein one page data is stored in the memory cells connected with the bitlines.
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November 7, 2006
March 17, 2009
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