A semiconductor device tester includes a parametric measurement unit (PMU) driver circuit that provides a DC test signal for testing a semiconductor device, and a feedback circuit that senses the DC test signal at an output of the PMU driver circuit and sends the sensed DC test signal to an input of the PMU driver circuit for compensating the DC test signal.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device tester comprising: a PMU driver circuit configured to provide a DC test signal for testing a semiconductor device; a first feedback circuit configured to sense a DC test signal directly from an output of the PMU driver circuit, wherein there are no intervening circuit elements between the output of the PMU driver circuit and a point at which the first feedback circuit senses the DC test signal; a second feedback circuit electrically connected to the semiconductor device, the second feedback circuit to sense the DC test signal near the semiconductor device; a third feedback circuit electrically connected across part of an output signal path of the PMU driver circuit, the third feedback circuit to sense a current output of the PMU driver circuit; and a switch to electrically connect one of the first feedback circuit, the second feedback circuit, and the third feedback circuit to an input of the PMU driver circuit; wherein the PMU driver circuit is configured to compensate for voltage or current based on which of the first feedback circuit, the second feedback circuit, and the third feedback circuit is electrically connected, via the switch, to the PMU driver circuit.
2. The semiconductor device tester of claim 1 , wherein the first feedback circuit comprises a conductor that is electrically connected to the output of the PMU driver circuit.
3. The semiconductor device tester of claim 1 , wherein the switch is connected to the output of the PMU driver circuit via the first feedback circuit.
4. The semiconductor device tester of claim 1 , wherein the switch is connected to the output of the PMU driver circuit and to the input of the PMU driver circuit via the first feedback circuit.
5. The semiconductor device tester of claim 1 , wherein the PMU driver circuit is configured to compare the DC test signal to a signal present at an input of the PMU driver circuit.
6. The semiconductor device tester of claim 1 , wherein the PMU driver circuit is configured to adjust the DC test signal output by the PMU driver circuit to compensate for a difference between the DC test signal and a signal present at the input of the PMU driver circuit.
7. The semiconductor device tester of claim 1 , wherein the part of the output signal path comprises a resistor.
8. The semiconductor device tester of claim 1 , wherein the second feedback circuit is electrically connected to the semiconductor device via at least one circuit element that has an impedance.
9. A method of testing a semiconductor device, the method comprising: electrically connecting, via a switch, one of a first feedback circuit, a second feedback circuit, and a third feedback circuit to an input of a PMU driver circuit, the PMU driver circuit providing a DC test signal for testing a semiconductor device; when the first feedback circuit is electrically connected via the switch to the input of the PMU driver circuit, sensing a DC test signal directly from an output of the PMU driver circuit, wherein there are no intervening circuit elements between the output of the PMU driver circuit and a point at which the first feedback circuit senses the DC test signal; when the second feedback circuit is electrically connected via the switch to the input of the PMU driver circuit, sensing the DC test signal near the semiconductor device; when the third feedback circuit is electrically connected via the switch to the input of the PMU driver circuit, sensing a current output of the PMU driver circuit across part of an output signal path of the PMU driver circuit; and the PMU driver circuit compensating for voltage or current based on which of the first feedback circuit, the second feedback circuit, and the third feedback circuit is electrically connected, via the switch, to the PMU driver circuit.
10. The method of claim 9 , wherein compensating comprises comparing the DC test signal to a signal present at the input of the PMU driver circuit.
11. The method of claim 9 , wherein compensating comparing a voltage of the DC test signal to a voltage of a signal present at the input of the PMU driver circuit.
12. The method of claim 9 , wherein compensating comprises adjusting the DC test signal provided by the PMU driver circuit to compensate for a difference between the DC test signal and a signal present at the input of the PMU driver circuit.
13. A semiconductor device tester, comprising: a PE stage configured to provide an alternating current (AC) test signal for testing a semiconductor device; and a PMU stage configured to provide a direct current (DC) test signal for testing the semiconductor device, the PMU stage comprising: a PMU driver circuit configured to receive a DC input signal and to produce the DC test signal, a first feedback circuit configured to sense the DC test signal directly from an output of the PMU driver circuit, wherein there are no intervening circuit elements between the output of the PMU driver circuit and a point at which the first feedback circuit senses the DC test signal; a second feedback circuit electrically connected to the semiconductor device, the second feedback circuit to sense the DC test signal near the semiconductor device; a third feedback circuit electrically connected across part of an output signal path of the PMU driver circuit, the third feedback circuit to sense a current output of the PMU driver circuit; and a switch to electrically connect one of the first feedback circuit, the second feedback circuit, and the third feedback circuit to an input of the PMU driver circuit; wherein the PMU driver circuit is configured to compensate for voltage or current based on which of the first feedback circuit, the second feedback circuit, and the third feedback circuit is electrically connected, via the switch, to the PMU driver circuit.
14. The semiconductor tester of claim 13 , wherein the output signal path comprises an impedance element electrically connected between the output of the PMU driver circuit and the semiconductor device.
15. The semiconductor tester of claim 13 , wherein the PE stage is configured to provide a PMU current test signal to the semiconductor device under test and is also configured to sense a response from the semiconductor device under test.
16. The semiconductor device tester of claim 13 , wherein the PMU driver circuit is configured to compensate by comparing the DC test signal to a signal present at the input of the PMU driver circuit.
17. The semiconductor device tester of claim 13 , wherein the PMU driver circuit is configured to compensate by comparing a voltage of the DC test signal to a voltage of a signal present at the input of the PMU driver circuit.
18. The semiconductor device tester of claim 13 , wherein the PMU driver circuit is configured to compensate by adjusting the DC test signal provided by the PMU driver circuit to compensate for a difference between the DC test signal and a signal present at the input of the PMU driver circuit.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 21, 2005
March 24, 2009
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