A semiconductor device includes a memory cell array and a command interface that is configured to receive a command from outside of the semiconductor memory device. The command interface is further configured to interpret the received command and to determine if the received command is a continuous operation command. The command interface outputs a command signal corresponding to the command and at least one flag signal that indicates a continuous operation section if the command is a continuous operation command. A control unit is configured to receive the command signal and the at least one flag signal output from the command interface, and to generate a pump control signal based on the received command signal and the at least one flag signal. A charge pump is configured to generate a voltage in response to the pump control signal for use in accessing the memory cell array to read write and/or erase data.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor memory device comprising: a memory cell array; a command interface configured to receive a command from outside of the semiconductor memory device, to interpret the received command to determine if the received command is a continuous operation command, and to output a command signal corresponding to the command and at least one flag signal indicating a continuous operation section if the command is a continuous operation command, the command interface comprising: a command decoder configured to receive the command, to interpret the received command, and to output the command signal corresponding to the command to the control unit; and a flag signal generation unit configured to receive the command interpreted by the command decoder and to output to the control unit the at least one flag signal indicating whether the command is a continuous operation command and indicating a continuous operation section if the command is a continuous operation command; a control unit configured to receive the command signal and the at least one flag signal output from the command interface and to generate a pump control signal based on the received command signal and the at least one flag signal; and a charge pump configured to generate a voltage in response to the pump control signal for use in accessing the memory cell array to read, write, and/or erase data.
2. The semiconductor memory device of claim 1 , wherein the flag signal generation unit comprises: a command register configured to receive and to store the command signal; a continuous operation command storing unit configured to store information on the continuous operation commands; and a comparison unit configured to search the information on the continuous operation commands stored in the continuous operation command storing unit for a command signal stored in the command register and to generate the at least one flag signal based on a search result.
3. The semiconductor memory device of claim 1 , wherein the flag signal generation unit is configured to generate a first flag signal having a first logic level when a first operation section of the continuous operation command starts.
4. The semiconductor memory device of claim 3 , wherein the flag signal generation unit is further configured to generate a second flag signal having a first logic level when a last operation section of the continuous operation command starts.
5. The semiconductor memory device of claim 4 , wherein the control unit in response to the second flag signal is configured to output a recovery signal to recover the charge pump to the charge pump.
6. The semiconductor memory device of claim 1 , wherein the continuous operation command comprises at least one of a cache read, a cache program, and a burst mode command.
7. The semiconductor memory device of claim 1 , wherein the semiconductor memory device is a flash memory.
8. A method for controlling a charge pump of a semiconductor memory device, comprising: receiving a command from outside of the semiconductor memory device; interpreting the received command to determine if the received command is a continuous operation command; generating inside the semiconductor memory device a command signal corresponding to the command and at least one flag signal indicating a continuous operation section if the command is a continuous operation command; generating a pump control signal responsive to the command signal and the at least one flag signal; and generating a voltage responsive to the pump control signal for accessing a memory cell array to read, write, and/or erase data; wherein generating the at least one flag signal comprises: searching information on continuous operation commands stored in a continuous operation command storing unit for the command signal; and generating the at least one flag signal based on a search result.
9. The method of claim 8 , wherein generating the at least one flag signal comprises generating a first flag having a first logic level when a first operation section of the continuous operation command starts.
10. The method of claim 9 , wherein generating the at least one flag signal further comprises generating a second flag signal having the first logic level when a last operation section of the continuous operation command starts.
11. The method of claim 10 , wherein generating the pump control signal responsive to the at least one flag signal comprises generating the pump control signal to recover the charge pump in response to the second flag signal.
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November 30, 2006
March 24, 2009
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