The present invention provides a novel method for increasing the amount of deuterium incorporated into trap sites of a transistor device during a deuterium passivation anneal by electrically pre-stressing the fabricated device prior to a deuterium anneal. The method of the present invention equally applies to SOI and CMOS technology. As a result, the incorporation of more deuterium during a deuterium anneal in the process flow reduces the number of undesirable trap sites.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A transistor comprising: a semiconductor substrate; a buried oxide layer formed within said substrate; a trench isolation region formed within said substrate; a source region; a drain region; a channel region; passivated trap site regions comprising trap sites of at least said buried oxide layer and said channel region, said passivated trap site regions formed by (a) applying different voltages to said source region and said drain region to electrically stress and thereby remove a first passivating species from said trap sites, and (b) after removing said first passivating species from said trap sites, passivating said trap sites with a second passivating species; and a transistor gate formed over said channel region, wherein, due to steps (a) and (b), a percentage of said trap sites passivated by said second passivating species near said drain region is greater than a percentage of said trap sites passivated by said second passivating species near said source region.
2. The transistor of claim 1 , wherein said second passivating species are deuterium atoms.
3. The transistor of claim 1 , wherein said passivated trap site regions comprise first, second, and third trap site regions, said buried oxide layer comprises said first trap site region, said trench isolation region comprises said second trap site region, and said channel region comprises said third trap site region.
4. The transistor of claim 1 , wherein step (a) further comprises: applying an operational supply voltage of the transistor Vcc to the drain region; and applying a gate voltage of about Vcc/2 to the transistor gate.
5. The transistor of claim 1 3 , wherein said second trap site region is located along a trench isolation region sidewall.
6. The transistor of claim 1 3 , wherein said second trap site region is located between said trench isolation region and said buried oxide layer.
7. The transistor of claim 3 , wherein said second trap site region is located between said trench isolation region and said channel region.
8. The transistor of claim 3 , wherein said third trap site region is located between said channel region and said transistor gate.
9. The transistor of claim 3 , wherein said first trap site region is located between said buried oxide layer and said channel region.
10. A transistor comprising: a source region; a drain region; a channel region; a multi-layer gate formed over a semiconductor substrate, wherein said multi-layer gate comprises an insulating layer and at least one conductive layer; an oxide layer formed within said substrate; at least one trench isolation region; and at least one electrically pre-stressed region comprising trap sites, said electrically pre-stressed region formed by (a) applying an electrical current from said source region to said drain region to remove hydrogen atoms from said trap sites, and (b) immediately re-passivating said trap sites with a passivating species more resistant to hot carriers than said hydrogen atoms, wherein steps (a) and (b) cause portions of said electrically pre-stressed region near said drain region to have a higher concentration of said re-passivated trap sites than portions of said electrically pre-stressed region near said source region.
11. The transistor of claim 10 , wherein said passivating species is at least one deuterium atom.
12. The transistor of claim 10 , wherein said electrically pre- stressed stressed region has been electrically stressed at less than 650 ° C.
13. The semiconductor device of claim 10 , wherein said electrically pre-stressed transistor has been electrically stressed under peak substrate conditions of said transistor.
14. The transistor of claim 13 , wherein said electrically pre- stressed transistor has been electrically stressed by a gate voltage substantially equal to Vd/2, where Vd is a drain voltage of said transistor.
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September 1, 2005
March 31, 2009
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