A method evaluating threshold of a data cell in a memory device including a programming locus coupled with the data cell for receiving a programming signal setting a stored signal level in the data cell and responding to a read signal to indicate the stored signal at a read locus; includes the steps of: (a) in no particular order; (1) selecting a test threshold signal; and (2) setting a read signal at a non-read level; (b) applying the test threshold signal to the programming locus; (c) cycling the read signal between a read level and a non-read level while applying the test threshold signal to the programming locus to present at least two test signals at the read locus when the read signal is at the read level; and (d) while cycling, observing whether the at least two test signals manifest a difference greater than a predetermined amount.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for evaluating a memory storage device, comprising the steps of: applying a low READ signal to the memory storage device; while applying said low READ signal to the memory storage device, applying a “0” to a programming node of the memory storage device; while applying the “0” to a programming node of the memory storage device, applying a high READ signal to the memory storage device and measuring a first output voltage of the memory storage device; applying the low READ signal to the memory storage device; while applying said low READ signal to the memory storage device, applying a test signal to a programming node of the memory storage device, said test signal being less than a designed threshold level; while applying the test signal to a programming node of the memory storage device, applying the high READ signal to the memory storage device and measuring a second output voltage of the memory storage device; comparing said first output voltage to said second output voltage, wherein a difference between said first output voltage to said second output voltage less than a predetermined amount indicates proper configuration of the memory storage device.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 31, 2007
April 7, 2009
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