A semiconductor device includes a gate insulating film which is formed on the major surface of a semiconductor substrate, a gate electrode which is formed on the gate insulating film, a first offset-spacer which is formed in contact with one side surface of the gate electrode, a first spacer which is formed in contact with the other side surface of the gate electrode, a second spacer which is formed in contact with the first offset-spacer, and source and drain regions which are formed apart from each other in the major surface of the semiconductor substrate below the first and second spacers so as to sandwich the gate electrode and the first offset-spacer. The source region is formed at a position deeper than the drain region. The dopant concentration of the source region is higher than that of the drain region.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of manufacturing a semiconductor device comprising: forming an element isolation film in a major surface of a semiconductor substrate to form an element region; forming a dummy pattern layer on the semiconductor substrate in a prospective drain region; forming an offset-spacer material in the element region and on the dummy pattern layer; etching back the offset-spacer material, thereby forming a first offset-spacer in contact with a side wall of the dummy pattern layer; forming a gate insulating film and a gate electrode in contact with a side wall of the first offset-spacer; doping a dopant by using the gate electrode and the dummy pattern layer as a mask, thereby forming a first source region in the semiconductor substrate; removing the dummy pattern layer; and doping a dopant by using the gate electrode and the first offset-spacer as a mask, thereby forming a first drain region in the semiconductor substrate.
2. The method of manufacturing a semiconductor device according to claim 1 , wherein the first drain region is formed in the semiconductor substrate such that the first drain region is at a position shallower than the first source region in the semiconductor substrate.
3. The method of manufacturing a semiconductor device according to claim 1 , further comprising forming a first spacer on a side wall of the gate electrode and a second spacer on a side wall of the first offset-spacer after forming the first drain region.
4. The method of manufacturing a semiconductor device according to claim 3 , further comprising doping a dopant by using the first and the second spacer as a mask, thereby forming the second source region and the second drain region in the semiconductor substrate, the second source region and the second drain region being at positions deeper than the first source region.
5. The method of manufacturing a semiconductor device according to claim 3 , further comprising doping a dopant by using the first and the second spacer as a mask, thereby forming a fourth drain region at a position shallower than the first source region and deeper than the first drain region, and forming an LDD structure on only a drain side.
6. The method of manufacturing a semiconductor device according to claim 1 , further comprising forming a second offset-spacer in the element region on the side wall of the gate electrode after forming the gate insulating film and the gate electrode.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 17, 2006
April 14, 2009
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