Pulse detector which employs a self-resetting pulse amplifier

1. A circuit comprising: an optical detector for detecting an optical pulse and generating therefrom a current pulse on an output; and a pulse detector circuit having an input electrically connected to the optical detector and having an output for outputting a detection pulse in response to receiving the current pulse on its input, said detection pulse characterized by a change in voltage, said pulse detector circuit including: a resettable amplifier including an input for receiving the current pulse from the optical detector, a reset terminal for resetting the amplifier after the amplifier receives the current pulse on its input, and an output for outputting a signal from which the detection pulse is derived; and a reset delay chain connected to receive the detection pulse from the output of the pulse detector circuit and to provide an electrical path over which the change in voltage that characterizes the detection pulse propagates to produce at the reset terminal of the resettable amplifier a feedback signal that is delayed relative to the detection pulse and which resets the resettable amplifier, wherein the resettable amplifier is configured to switch from a first state to a second state upon receiving the current pulse and to switch back to the first state in response to being reset by the feedback signal.

2. The circuit of claim 1 , further comprising an optical waveguide, wherein the optical detector is arranged to detect the optical pulse as it travels through the optical waveguide.

3. The circuit of claim 1 , wherein the pulse detector further comprises a biasing circuit and the resettable amplifier includes a current load that is biased by the biasing circuit.

4. The circuit of claim 3 , wherein the biasing circuit is a supply-independent biasing circuit.

5. The circuit of claim 1 , wherein the pulse detector circuit further includes an output stage which has an input for receiving the output signal of the resettable amplifier and an output for outputting the detection pulse.

6. The circuit of claim 5 , wherein the output stage includes an output inverter.

7. The circuit of claim 6 , wherein the output inverter has an input which is the input of the output stage and has an output which is the output of the output stage.

8. The circuit of claim 7 , wherein the reset delay chain is connected between the output of the output stage and the reset terminal.

9. The circuit of claim 3 , wherein the current load is a MOSFET.

10. The circuit of claim 1 , wherein the resettable amplifier includes a MOSFET configured as a common-source stage.

11. The circuit of claim 3 , wherein the biasing circuit includes a current mirror.

12. The circuit of claim 11 , wherein the biasing circuit is a resistorless biasing circuit.

13. The circuit of claim 11 , wherein the biasing circuit includes a first and second transistor configured as a first current mirror and a third and fourth transistor configured as a second current mirror.

14. The circuit of claim 13 , wherein the first, second, third and fourth transistors are MOSFETs.

15. The circuit of claim 14 , wherein the first and second MOSFETs have channel lengths that are equal and wherein the third and fourth MOSFETs have channel lengths that are unequal.

16. The circuit of claim 15 , wherein the current load is a MOSFET and wherein the first and second MOSFETs and the current load MOSFET have their gate terminals electrically connected together.

17. The circuit of claim 1 , wherein the reset delay chain is a plurality of inverters connected in series.

18. The circuit of claim 17 , wherein the reset delay chain is made up of an odd number of inverters connected in series.

19. The circuit of claim 1 , wherein the optical detector is directly connected to the input of the resettable amplifier.

20. A method of detecting an optical pulse traveling through an optical waveguide, said method comprising: converting the optical pulse traveling through the optical waveguide to a current pulse; converting the current pulse to a voltage pulse; biasing a resettable amplifier in a first state which is in a high gain region of operation; using the voltage pulse to cause the resettable amplifier to switch from the first state to a second state and thereby generate a detection pulse which is characterized by a voltage transition; propagating the voltage transition through a delay circuit to generate a feedback signal that is delayed relative to the detection pulse; and using the feedback signal to reset the resettable amplifier from the second state back to the first state.

21. A circuit comprising: an optical detector for detecting optical clock pulses and generating therefrom corresponding electrical pulses on an output; and a pulse detector circuit having an input electrically connected to the optical detector and having an output for outputting electrical clock pulses in response to receiving the electrical pulses on its input, each of said electrical clock pulses characterized by a corresponding change in voltage, said pulse detector circuit including: a resettable amplifier including an input for receiving the electrical pulses from the optical detector, a reset terminal for resetting the amplifier after the amplifier receives each of the electrical pulses on its input, and an output for outputting a signal from which the electrical clock pulses are derived; and a reset delay chain connected to receive the electrical clock pulses at the output of the pulse detector circuit and to provide for each of the received electrical clock pulses an electrical path over which the change in voltage that characterizes that received electrical clock pulse propagates to produce at the reset terminal of the resettable amplifier a feedback signal that is delayed relative to that received electrical clock pulse and which resets the resettable amplifier, wherein the resettable amplifier is configured to switch from a first state to a second state upon receiving each of the electrical pulses and to switch back to the first state in response to being reset by the feedback signal.

22. A method of detecting optical clock pulses traveling through an optical waveguide, said method comprising: converting the optical clock pulses to corresponding electrical pulses; biasing a resettable amplifier in a first state which is in a high gain region of operation; in response to each of the electrical pulses, (1) causing the resettable amplifier to switch from the first state to a second state and thereby generate a detection pulse which is characterized by a voltage transition, (2) propagating the voltage transition through a delay circuit to generate a feedback signal, and (3) using the feedback signal to reset the resettable amplifier from the second state back to the first state.

23. The circuit of claim 1 , further comprising a biasing circuit that biases the resettable amplifier in a high gain region during operation, said first state being in the high gain region.

24. The circuit of claim 21 , further comprising a biasing circuit that biases the resettable amplifier in a high gain region during operation, said first state being in the high gain region.