A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory device comprising: circuitry operable in a write calibration mode as a phase detector, the circuitry comprising: a first input to receive a clock signal, a second input to receive a calibration sequence from a memory controller, and an output to generate a signal representing a phase difference between the clock signal and the received calibration sequence; and a transmitter to transmit the generated signal to the memory controller.
2. The memory device of claim 1 , wherein the calibration sequence is a data pattern received from the memory controller.
3. The memory device of claim 1 , wherein the first input receives the clock signal from a phase-locked loop (PLL) or delay-locked loop (DLL) on the memory device.
4. A memory device comprising: clock circuitry to distribute a clock signal; calibration circuitry operable in a calibration mode and comprising a phase detector, the phase detector comprising: a first input coupled to the clock circuitry to receive a clock signal, a second input to receive a calibration sequence via a signal path associated with transmitting write data between a memory controller and the memory device, and an output to provide phase data representing a phase difference between the clock signal and the received calibration sequence; and a transmitter to transmit the phase data to the memory controller.
5. The memory device of claim 4 , wherein the calibration sequence is a data pattern received from the memory controller.
6. The memory device of claim 4 , wherein the signal path associated with transmitting write data is a data bus.
7. The memory device of claim 4 , wherein the clock circuitry comprises a PLL or DLL.
8. A method of calibrating write operations in a memory system including a memory controller and a memory device, the method comprising: receiving at the memory device a calibration sequence transmitted by the memory controller; generating a signal representing a phase difference between the received calibration sequence and a clock signal; transmitting the generated signal to the memory controller; and adjusting a timing offset for write operations in accordance with the generated signal.
9. The method of claim 8 , further including repeating the receiving, generating, transmitting, and adjusting for each of a plurality of memory devices in the memory system, wherein the timing offsets for the plurality of memory devices are independent.
10. The method of claim 8 , wherein the calibration sequence is a data pattern.
11. The method of claim 8 , wherein the clock signal is generated by a phase-locked loop (PLL) or delay-locked loop (DLL) on the memory device.
12. A memory system comprising: a first memory device; a second memory device; and a memory controller coupled to the first and second memory devices; the memory controller including calibration circuitry to adjust a write timing offset for each memory device, wherein each write timing offset corresponds to a phase difference signal received from a corresponding memory device; and wherein a respective phase difference signal represents a phase difference between a receive clock signal in the corresponding memory device and a calibration sequence.
13. The memory system of claim 12 , wherein the write timing offset for the first memory device is independent of the write timing offset for the second memory device.
14. The memory system of claim 12 , wherein the first memory device comprises: circuitry operable in a write calibration mode as a phase detector, the circuitry comprising: a first input to receive the receive clock signal, a second input to receive the calibration sequence from the memory controller, and an output to generate a signal according to a phase difference between the receive clock signal and the received calibration sequence; and a transmitter to transmit the generated signal to the memory controller.
15. The memory system of claim 14 , wherein the first input receives the receive clock signal from a phase-locked loop (PLL) or delay-locked loop (DLL) on the first memory device.
16. The memory system of claim 12 , wherein the first memory device comprises: clock circuitry to distribute the receive clock signal; calibration circuitry operable in a calibration mode and comprising a phase detector, the phase detector comprising: a first input coupled to the clock circuitry to receive the receive clock signal, a second input to receive the calibration sequence via a signal path associated with transmitting write data between the memory controller and the first memory device, and an output to provide phase data corresponding to a phase difference between the receive clock signal and the received calibration sequence; and a transmitter to transmit the phase data to the memory controller.
17. The memory system of claim 16 , wherein the clock circuitry in the first memory device comprises a PLL or DLL.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 5, 2006
May 19, 2009
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