A method of manufacturing an electronic device, which can obtain sufficient manufacturing margins and reduce a defect rate by compensating for a threshold voltage variation caused by the variation of a critical dimension (CD) of a gate electrode. An ion implanter controller and an ion implantation system perform the method. In the method, an ion implantation recipe for forming a junction contact plug of a transistor formed on the wafer is adjusted based on the measured CD. Then, ions are implanted into the wafer by using the adjusted ion implantation recipe. All defects that may occur in the transistor during previous manufacturing steps can be repaired after the transistor is formed, thus enhancing manufacturing margins.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of manufacturing an electronic device comprising: measuring a critical dimension (CD) of a gate electrode formed on a wafer; adjusting an ion implantation recipe to form a junction contact plug of a transistor formed on the wafer, based on the measured CD; and implanting ions into the wafer to form the junction contact plug using the adjusted ion implantation recipe.
2. The method of claim 1 , wherein in the adjusting of the ion implantation recipe, the ion implantation recipe is adjusted to compensate for a threshold voltage variation caused by a difference between a target CD and the measured CD.
3. The method of claim 1 , wherein the ion implantation recipe comprises an ion implantation dose.
4. The method of claim 1 , wherein the CD of the gate electrode is a line width of the gate electrode.
5. The method of claim 1 , wherein the measuring of the CD comprises: forming gate electrodes on the wafer; determining a plurality of measurement positions on the wafer; measuring CDs of two or more adjacent gate electrodes at each of the plurality of measurement positions and then averaging the measured CDs to obtain an average CD at each of the plurality of measurement positions; and obtaining a final CD by averaging the average CD at each of the plurality of measurement positions.
6. The method of claim 5 , wherein obtaining the average CD at each of the plurality of measurement positions comprises: measuring CDs of four adjacent gate electrodes at each of the plurality of measurement positions; and averaging the CDs of the four adjacent gate electrodes at each of the plurality of measurement positions.
7. The method of claim 1 , wherein the adjusted ion implantation recipe is selected from a set of discrete ion implantation recipes that are quantified to compensate for a threshold voltage of the transistor with respect to each of a plurality of equally divided sections obtained by dividing a maximum CD variation range within a manufacturing specification range with a constant interval.
8. The method of claim 1 , wherein the ion implantation recipe is an output value obtained when the measured CD is input to a mathematical model to make a threshold voltage of the transistor with the measured CD to be the same as the threshold voltage of the transistor with a target CD.
10. The method of claim 1 , wherein the measuring the CD is performed by a measurement device, and the adjusting the ion implantation recipe is performed by an ion implanter controller adapted to adjust the ion implantation recipe to form a junction contact plug of a transistor by using the measured CD.
11. The method of claim 1 , wherein the implanting ions comprises: forming a junction area of the transistor in the wafer; forming an insulation layer on the wafer; forming a contact hole in the insulation layer to expose the junction area therethrough; and forming the junction contact plug of the transistor by implanting ions into the junction area exposed by the contact hole with the adjusted ion implantation recipe.
12. The method of claim 1 , wherein the implanting ions comprises: forming spacers at sidewalls of the gate electrode and forming a junction area of the transistor in the wafer; forming an insulation layer on the wafer; forming a self-aligned contact hole self-aligned with the spacer in the insulation layer to expose the junction area therethrough; and forming the junction contact plug of the transistor by implanting ions into the junction area exposed by the self-aligned contact hole with the adjusted ion implantation recipe.
13. The method of claim 1 , wherein the gate electrode is a gate electrode of a memory cell of a DRAM, an SRAM, a flash memory, an FRAM, an MRAM, a PRAM, or any combination thereof.
14. An ion implanter controller comprising: a measurement device adapted to measure a CD of a gate electrode formed on a wafer; an ion implantation recipe adjustment unit structured and arranged to adjust an ion implantation recipe to form a junction contact plug of a transistor based on the measured CD of the gate electrode; and a transmission unit structured and arranged to transmit an operational command modified according to the adjusted ion implantation recipe to an ion implanter.
15. The ion implantation controller of claim 14 , wherein the ion implantation recipe adjustment unit is adapted to compensate for a threshold voltage variation caused by a difference between a target CD and the measured CD.
16. The ion implantation controller of claim 14 , wherein the ion implantation recipe comprises an ion implantation dose.
17. The ion implantation controller of claim 14 , wherein the CD of the gate electrode is a line width of the gate electrode.
18. The ion implantation controller of claim 14 , wherein the ion implantation recipe adjustment unit comprises: an input unit adapted structured and arranged to receive CDs of two or more adjacent gate electrodes measured at each of a plurality of measurement positions, which are measured by the measurement device; a first calculation unit structured and arranged to average the CDs of the two or more adjacent gate electrodes corresponding to each of the plurality of measurement positions, and to average the resulting CD averages to obtain a final CD; a second calculation unit structured and arranged to obtain a difference between the final CD and a target CD; and a recipe selection unit structured and arranged to select the ion implantation recipe from a set of discrete ion implantation recipes that are quantified to compensate a threshold voltage of the transistor with respect to each of a plurality of equally divided sections that may be obtained by dividing a maximum CD variation range within a manufacturing specification range with a constant interval.
19. The ion implantation controller of claim 14 , wherein the ion implantation recipe adjustment unit comprises: an input unit structured and arranged to receive CDs of two or more adjacent gate electrodes measured at each of a plurality of measurement positions, which are measured by a measurement device; a first calculation unit structured and arranged to average the CDs of the two or more adjacent gate electrodes corresponding to each of the plurality of measurement positions, and to average the resulting CD averages to obtain a final CD; and a second calculation unit structured and arranged to use the final CD and is composed of a mathematical model that enables a threshold voltage to be the same as that of a target CD of the gate electrode.
20. The ion implantation controller of claim 14 , wherein the gate electrode is a gate electrode of a memory cell of a DRAM, an SRAM, a flash memory, an FRAM, an MRAM, a PRAM, or any combination thereof.
21. An ion implantation system comprising: a measurement device structured and arranged to measure a CD of a gate electrode formed on a wafer; an ion implanter controller structured and arranged to adjust an ion implantation recipe to form a junction contact plug of a transistor based on the measured CD of the gate electrode, and to transmit an operational command modified according to the adjusted ion implantation recipe; and an ion implanter structured and arranged to perform junction contact plug ion implantation according to the operational command.
22. The ion implantation system of claim 21 , wherein the ion implanter controller is adapted to adjust the ion implantation recipe to compensate for a threshold voltage variation caused by a difference between a target CD and the measured CD.
23. The ion implantation system of claim 21 , wherein the ion implantation recipe comprises an ion implantation dose.
24. The ion implantation system of claim 21 , wherein the CD of the gate electrode is a line width of the gate electrode.
25. The ion implantation system of claim 21 , wherein the ion implanter controller comprises: an input unit structured and arranged to receive CDs of two or more adjacent gate electrodes measured at each of a plurality of measurement positions, which are collected by an equipment server, from a measurement device; a first calculation unit structured and arranged to average the CDs of the two or more adjacent gate electrodes corresponding to each of the plurality of measurement positions, and to average the resulting CD averages to obtain a final CD; a second calculation unit structured and arranged to obtain a difference between the final CD and a target CD; and a recipe selection unit structured and arranged to select the ion implantation recipe from a set of discrete ion implantation recipes that are quantified to compensate a threshold voltage of the transistor with respect to each of a plurality of equally divided sections that may be obtained by dividing a maximum CD variation range within a manufacturing specification range with a constant interval.
26. The ion implantation system of claim 21 , wherein the ion implanter controller comprises: an input unit structured and arranged to receive CDs of two or more adjacent gate electrodes measured at each of a plurality of measurement positions, which are measured by the measurement device; a first calculation unit structured and arranged to average the CDs of the two or more adjacent gate electrodes corresponding to each of the plurality of measurement positions, and to average the resulting CD averages to obtain a final CD; and a second calculation unit structured and arranged to use the final CD and is composed of a mathematical model that enables a threshold voltage to be the same as that of a target CD of the gate electrode.
27. The ion implantation system of claim 21 , wherein the gate electrode is a gate electrode of a memory cell of a DRAM, an SRAM, a flash memory, an FRAM, an MRAM, a PRAM, or any combination thereof.
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February 7, 2005
May 26, 2009
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