A bumping process comprises forming a passivation layer having a planarized surface covering a pad on a substrate, forming a hole penetrating through the passivation layer to expose a contact surface of the pad, and forming a bump on the contact surface and planarized surface. The planarized surface will provide a larger effective area for pressing, thereby minimizing the pad, enhancing the mechanical strength at the peripheral of the pad, providing more selection flexibility for anisotropic conductive film, reducing the possibilities of short circuit and current leakage within the bump gap, and increasing the yield of the pressing process and the conductive quality of the bump.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A bump structure for electrically coupling to a pad on a substrate, the bump structure comprising: a passivation layer having a planarized surface extending thereon to cover a portion of the pad, the planarized surface extending along a plane substantially parallel to the pad; a contact surface on the pad; and a bump contacting the contact surface and planarized surface, the bump extending laterally to at least a peripheral extent of the pad; whereby the bump defines an effective region extending over the planarized surface of the passivation layer for flip chip engagement of a second substrate.
2. The bump structure of claim 1 , wherein the passivation layer comprises: a first layer having a planarized surface; and a second layer on the first layer.
3. The bump structure of claim 2 , wherein the second layer comprises at least one layer harder than the first layer.
4. The bump structure of claim 2 , wherein the first layer comprises silicon dioxide or silicon oxide, and the second thin film layer comprises silicon nitride or silicon oxy nitride.
5. The bump structure of claim 2 , wherein the first layer comprises silicon dioxide or silicon oxide, and the second layer comprises layers of silicon nitride or silicon oxy nitride and silicon dioxide or silicon oxide in stack.
6. The bump structure of claim 1 , wherein the passivation layer comprises: a first layer; and a second layer having a planarized surface on the first layer.
7. The bump structure of claim 6 , wherein the second layer comprises at least one layer harder than the first layer.
8. The bump structure of claim 6 , wherein the first layer comprises silicon dioxide or silicon oxide, and the second layer comprises silicon nitride or silicon oxy nitride.
9. The bump structure of claim 6 , wherein the first layer comprises silicon dioxide or silicon oxide, and the second layer comprises layers of silicon nitride or silicon oxy nitride and silicon dioxide or silicon oxide in stack.
10. The bump structure of claim 1 , wherein the passivation layer comprises two layers sandwiching a third layer harder than the two layers.
11. The bump structure of claim 1 , wherein the contact surface has a stripe shape.
12. The bump structure of claim 1 , wherein the bump comprises: an under bump metallization having a first area on the contact surface and a second area on the planarized surface, the second area greater than the first area; and a conductive bump on the under bump metallization.
13. The bump structure of claim 12 , wherein the conductive bump comprises: a gold film on the under bump metallization; and a gold bump on the gold film.
14. The bump structure of claim 1 , wherein the bump comprises: an under bump metallization on the contact surface and a planarized surface; and a conductive bump contacting the under bump metallization, the conductive bump having a planarized surface on an opposite side to the under bump metallization.
15. The bump structure of claim 1 , wherein the bump has a larger area than the pad.
16. A bump pressing structure for electrically coupling a pad on a first substrate to a wire on a second substrate, the bump pressing structure comprising: a passivation layer having a planarized surface extending to cover a portion of the pad, the planarized surface extending along a plane substantially parallel to the pad; a bump contacting a contact surface of the pad and the planarized surface, the bump having a planarized surface facing the planarized surface of the passivation layer, the bump extending laterally to at least a peripheral extent of the pad, whereby the planarized surface of the bump defines an effective region extending over the planarized surface of the passivation layer for flip chip engagement of the second substrate; and a plurality of conductive particles compressed between the planarized surface of the bump and the wire.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 18, 2008
June 9, 2009
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