A dynamic random access memory (“DRAM”) device includes a pair of internal address buses that are selectively coupled to an external address bus by an address multiplexer, and a pair of internal data buses that are selectively coupled to an external data bus by a data multiplexer. The DRAM device also includes a bank multiplexer for each bank of memory cells that selectively couples one of the internal address buses and one of the internal data buses to the respective bank of memory cells. Select signals generated by a command decoder cause the multiplexers to select alternate internal address and data buses responsive to each memory command received by the command decoder.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory device, comprising: an external port adapted to receive memory command signals, memory address signals and write data signals and to transmit read data signals from the memory device; a plurality of internal address buses; an address coupling circuit operable to couple memory address signals corresponding to the memory addresses received by the external port to a selected one of the internal address buses; a plurality of banks of memory cells coupled to a respective one of the internal address buses; a bank coupling circuit for each of the banks of memory cells, the bank coupling circuit being operable to couple the memory address signals from each of the internal address buses to the respective bank; a data coupling circuit operable to couple the write data signals from the external port to the banks and to couple the read data signals from the banks to the external data port; and a control circuit coupled to the address coupling circuit, the control circuit being operable to apply signals to the address coupling circuit to cause the address coupling circuit to select the internal address bus to which the address signals are coupled, the control circuit comprising: a flip-flop having a clock input coupled to receive a signal generated responsive to each of the memory command signals being applied to the external port; and a plurality of logic gates coupled to the flip-flop, each of the logic gates generating a respective signal that sequentially selects a respective one of the internal address buses each time the flip-flop toggles.
2. The memory device of claim 1 further comprising a command decoder receiving the memory commands from the external port and decoding the received commands to output corresponding command signals.
3. The memory device of claim 2 further comprising a command bus coupled to receive the command signals from the command decoder, and wherein each of the bank coupling circuits is further operable to couple the command signals from the command bus to the respective bank.
4. The memory device of claim 3 wherein each of the bank coupling circuits receives respective address signals indicative of an access to the respective bank and wherein each of the bank coupling circuits is operable to couple the command signals from the command bus to the respective bank responsive to receiving the address signal indicative of an access to the respective bank.
5. The memory device of claim 1 wherein the address coupling circuit comprises an address multiplexer having an input bus port coupled to receive the memory addresses from the external port and a plurality of output bus ports coupled to respective ones of the plurality of internal address buses.
6. A memory device, comprising: an external port adapted to receive memory command signals, memory address signals and write data signals and to transmit read data signals from the memory device; a plurality of internal bi-directional data buses that are isolated from each other; a data coupling circuit operable to couple write data signals corresponding to write data from the external port to a selected one of the internal data buses, the data coupling circuit further being operable to couple read data signals corresponding to read data from a selected one of the internal data buses to the external port; a plurality of banks of memory cells coupled to a respective one of the internal data buses; a bank coupling circuit for each of the banks of memory cells, each of the bank coupling circuits being operable to couple the write data signals from the respective internal data bus to the respective bank and to couple the read data signals from the respective bank to the respective one of the internal data buses; an addressing circuitry receiving the memory address signals from the external port and being operable to select a memory location in at least one of the banks responsive to the received memory address signals; and control circuitry coupled to the data coupling circuit and the bank coupling circuit, the control circuitry being operable to apply signals to the data coupling circuit to cause the data coupling circuit to select the internal data bus to which the write data signals are coupled and from which the read data signals are coupled, the control circuitry comprising: a flip-flop having a clock input coupled to receive a signal generated responsive to the memory command signals applied to the external port; and a plurality of logic gates coupled to the flip-flop, each of the logic gates generating a respective signal that sequentially selects a respective one of the internal data buses each time the flip-flop toggles.
7. The memory device of claim 6 wherein the data coupling circuit comprises a data multiplexer having a first bus port coupled to the external port and a plurality of output bus ports coupled to respective ones of the plurality of internal data buses.
8. The memory device of claim 7 wherein the data multiplexer further comprises a second bus port coupled to a respective bank and a plurality of output bus ports coupled to respective ones of the plurality of internal data buses.
9. The memory device of claim 6 wherein the external port comprises a command bus port for receiving the memory command signals, an address bus port for receiving the memory address signals, and a data bus port for receiving the write data signals and outputting the read data signals from the memory device responsive to receiving the memory command signals and the memory address signals.
10. The memory device of claim 6 wherein the control circuitry comprises a plurality of logic gates operable to generate a respective signal that sequentially selects a respective one of the internal address buses.
11. A method of accessing data in a memory device, comprising: coupling a first memory command to the memory device; initiating a first memory access in a first bank of memory cells in the memory device responsive to the first memory command, the act of initiating the first memory access comprising prefetching data from the first bank of memory cells to transfer to an external device responsive to the first memory command; while the first memory access is being processed, coupling a second memory command to the memory device, the second memory command being different from the first memory command; and initiating a second memory access in a second bank of memory cells in the memory device responsive to the second memory command while the first memory access is being processed, the second bank being different from the first bank, the act of initiating the second memory access comprising initiating a prefetch of data from the second bank of memory cells responsive to the second memory command while data are being transferred to the external device responsive to the prefetching of data from the first bank of memory cells.
12. The method of claim 11 , further comprising: while the second memory access is being processed, coupling a third memory command to the memory device; and initiating a third memory access in the first bank of memory cells in the memory device responsive to the third memory command while the second memory access is being processed in the second bank of memory cells.
13. The method of claim 11 wherein the act of initiating the prefetch of data from the second bank of memory cells comprises coupling a memory command and a memory address to the memory device.
14. The method of claim 11 wherein each of the banks have a plurality of pages of memory cells, and wherein the act of prefetching data from the first bank of memory cells comprises prefetching data from less than an entire page of memory cells in the first bank, and wherein the act of initiating the prefetch of data from the second bank of memory cells comprises initiating a prefetch of data from less than an entire page of memory cells in the second bank.
15. A memory device, comprising: an external port adapted to receive memory command signals, memory address signals and write data signals and to transmit read data signals from the memory device; a plurality of internal address buses that are isolated from each other; an address coupling circuit operable to couple memory address signals corresponding to the memory addresses received by the external port to either one of the internal address buses; a plurality of internal bidirectional data buses that are isolated from each other; a data coupling circuit operable to couple write data signals corresponding to write data from the external port to either one of the internal data buses, the data coupling circuit further being operable to couple read data signals corresponding to read data from either one of the internal data buses to the external port; a plurality of banks of memory cells coupled to a respective one of the internal address buses; a bank coupling circuit for each of the banks of memory cells, the bank coupling circuit being operable to couple the memory address signals from either of the internal address buses to the respective bank; each of the bank coupling circuits being operable to couple the write data signals from either of the internal data buses to the respective bank and to couple the read data signals from the respective bank to either of the internal data buses; and a control circuit coupled to the address coupling circuit, the data coupling circuit and the bank coupling circuit, the control circuit being operable to apply signals to the address coupling circuit to cause the address coupling circuit to select either of the internal address buses to which the address signals are coupled, the control circuit further being operable to apply signals to the data coupling circuit to cause the data coupling circuit to select either of the internal data buses to which the write data signals are coupled and from which the read data signals are coupled, the control circuit comprising: a flip-flop having a clock input coupled to receive a signal generated responsive to each of the memory command signals being applied to the external port; and a plurality of logic gates coupled to the flip-flop, each of the logic gates generating a respective signal that sequentially selects a respective one of the internal address buses each time the flip-flop toggles.
16. The memory device of claim 15 further comprising a command decoder receiving the memory commands from the external port and decoding the received commands to output corresponding command signals.
17. The memory device of claim 16 further comprising a command bus coupled to receive the command signals from the command decoder, and wherein each of the bank coupling circuits is further operable to couple the command signals from the command bus to the respective bank.
18. The memory device of claim 17 wherein each of the bank coupling circuits receives respective address signals indicative of an access to the respective bank and wherein each of the bank coupling circuits is operable to couple the command signals from the command bus to the respective bank responsive to receiving the address signal indicative of an access to the respective bank.
19. The memory device of claim 15 wherein the address coupling circuit comprises an address multiplexer having an input bus port coupled to receive the memory addresses from the external port and a plurality of output bus ports coupled to respective ones of the plurality of internal address buses.
20. A memory device, comprising: an external port adapted to receive memory command signals, memory address signals and write data signals and to transmit read data signals from the memory device; a plurality of internal address buses that are isolated from each other; an address coupling circuit operable to couple memory address signals corresponding to the memory addresses received by the external port to either one of the internal address buses; a plurality of internal bidirectional data buses that are isolated from each other; a data coupling circuit operable to couple write data signals corresponding to write data from the external port to either one of the internal data buses, the data coupling circuit further being operable to couple read data signals corresponding to read data from either one of the internal data buses to the external port; a plurality of banks of memory cells coupled to a respective one of the internal address buses; a bank coupling circuit for each of the banks of memory cells, the bank coupling circuit being operable to couple the memory address signals from either of the internal address buses to the respective bank; each of the bank coupling circuits being operable to couple the write data signals from either of the internal data buses to the respective bank and to couple the read data signals from the respective bank to either of the internal data buses; and a control circuit coupled to the address coupling circuit, the data coupling circuit and the bank coupling circuit, the control circuit being operable to apply signals to the address coupling circuit to cause the address coupling circuit to select either of the internal address buses to which the address signals are coupled, the control circuit further being operable to apply signals to the data coupling circuit to cause the data coupling circuit to select either of the internal data buses to which the write data signals are coupled and from which the read data signals are coupled, the control circuit comprising: a flip-flop having a clock input coupled to receive a signal generated responsive to the memory command signals applied to the external port; and a plurality of logic gates coupled to the flip-flop, each of the logic gates generating a respective signal that sequentially selects a respective one of the internal data buses each time the flip-flop toggles.
21. The memory device of claim 20 further comprising a command decoder receiving the memory commands from the external port and decoding the received commands to output corresponding command signals.
22. The memory device of claim 21 further comprising a command bus coupled to receive the command signals from the command decoder, and wherein each of the bank coupling circuits is further operable to couple the command signals from the command bus to the respective bank.
23. The memory device of claim 20 wherein the address coupling circuit comprises an address multiplexer having an input bus port coupled to receive the memory addresses from the external port and a plurality of output bus ports coupled to respective ones of the plurality of internal address buses.
24. The memory device of claim 20 wherein the data coupling circuit comprises a data multiplexer having a first bus port coupled to the external port and a plurality of output bus ports coupled to respective ones of the plurality of internal data buses.
25. The memory device of claim 24 wherein the data multiplexer further comprises a second bus port coupled to a respective bank and a plurality of output bus ports coupled to respective ones of the plurality of internal data buses.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 10, 2007
June 16, 2009
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