A semiconductor chip 100 includes a logic unit and an analog unit 153. Furthermore, the semiconductor chip 100 includes a silicon substrate 101; a first insulating film 123 to a sixth insulating film 143 formed on the silicon substrate 101; and an annular seal ring 105 consisting of a first conductive ring 125 to a sixth conductive ring 145 buried in the first insulating film 123 to the sixth insulating film 143, which surrounds the periphery of the logic unit and the analog unit 153. In the seal ring region 106, there is formed a pn junction acting as a nonconducting part 104, which blocks conduction in a path from the logic unit, through the seal ring 105 to the analog unit 153.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device with a first device region and a second device region, comprising: a semiconductor substrate, an insulating interlayer formed on said semiconductor substrate, and an annular guard ring consisting of a conductive film buried in said insulating interlayer and surrounding the periphery of said first device region, wherein a nonconducting part blocking electric conduction in a path from said first device region, through said annular guard ring to said second device region is formed in a guard ring forming region, wherein there is formed a first diffusion layer having a same conductivity type as that in said semiconductor substrate in the vicinity of a surface of said semiconductor substrate; a second diffusion layer having an opposite conductivity type to that of said semiconductor substrate is formed in contact with a bottom surface of said first diffusion layer; a lateral periphery of said first diffusion layer is insulated; said annular guard ring is connected to a surface of said first diffusion layer; and said bottom surface of said first diffusion layer and a bottom surface of said second diffusion layer constitute said nonconducting part.
2. The semiconductor device according to claim 1 , wherein said annular guard ring comprises multiple conductive films adjacent to each other via said insulating interlayer; in a region comprising said nonconducting part, said annular guard ring comprises a plurality of columnar conductive plugs connected to said surface of said first diffusion layer; and in said region comprising said nonconducting part, said columnar conductive plugs are arranged as a diagonal lattice in the plane.
3. The semiconductor device according to claim 1 , wherein said second diffusion layer is apart from diffusion layers provided in said first and second device regions.
4. The semiconductor device according to claim 1 , wherein said semiconductor has a planar shape and said nonconducting part extends over a whole region immediately under said conductive film.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 9, 2005
June 23, 2009
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