A reduced storage capacitor is used for shrinking a memory cell in DRAM, and local bit line is divided into short line for reducing parasitic capacitance. For reading, a first reduced swing amplifier as a local sense amp reads the memory cell through the local bit line, and a second reduced swing amplifier as a global sense amp reads the local sense amp through a global bit line. With the multi-stage sense amps, time domain sensing scheme is realized such that a voltage difference in the local bit line is converted to a time difference, for differentiating high data and low data, and also fast read operation is realized. And write operation is executed by a reduced swing write driver. With reduced voltage swing, pseudo negative word line scheme is realized for retaining data, and power consumption is reduced. In addition, various alternative circuits and memory cell structures are implemented.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory device, comprising: a memory cell including a pass transistor and a capacitor; and a local sense amp including a first reduced swing amplifier and a write transistor, wherein the first reduced swing amplifier is used for limiting voltage swing of a local bit line connecting to the memory cell from a pre-charge voltage to a supply voltage, such that the first reduced swing amplifier is composed of a local pre amplifier and a local main amplifier, the local pre amplifier includes a local pre-charge transistor for pre-charging the local bit line to the pre-charge voltage, a local pre-amp transistor for detecting whether the local bit line is higher than the pre-charge voltage or not; and the local main amplifier includes a local pre-set transistor for pre-setting a local pre-amp node connecting to the local pre-amp transistor, a local main-amp transistor connecting to the local pre-amp node for driving a global bit line through a local select transistor; and the write transistor is connected to the local bit line for receiving a voltage output of the global bit line; and a global sense amp including a global read circuit, a global write circuit, a global latch circuit, a data transfer circuit and a data receive circuit, wherein the global read circuit is composed of a second reduced swing amplifier for limiting voltage swing of the global bit line, such that the second reduced swing amplifier is composed of a global pre amplifier and a global main amplifier, the global pre amplifier includes a global pre-charge transistor for pre-charging the global bit line to the pre-charge voltage, a global pre-amp transistor for detecting whether the global bit line is higher than the pre-charge voltage or not; and the global main amplifier includes a global pre-set transistor for pre-setting a global pre-amp node connecting to the global pre-amp transistor, a global main-amp transistor connecting to the global pre-amp node, and a global select transistor connecting to the global main-amp transistor serially; and the global write circuit is composed of a reduced swing write driver for driving the global bit line to the pre-charge voltage when writing data “0” and the supply voltage when writing data “1”; and the global latch circuit is connected to the global read circuit and the global write circuit; and the data transfer circuit receives a read output from the global latch circuit and transfers to a read line; and the data receive circuit receives a write input from a write line and sends to the global latch circuit; and a locking signal generator for locking the global select transistor of the global read circuit, wherein the locking signal generator includes a tunable delay circuit receiving an output from the global latch circuit.
2. The memory device of claim 1 , wherein the first reduced swing amplifier is composed of the local pre amplifier including the local pre-charge transistor for pre-charging the local bit line to the pre-charge voltage, the local pre-amp transistor for detecting whether the local bit line is higher than the pre-charge voltage or not; and the local main amplifier including the local pre-set transistor for pre-setting the local pre-amp node connecting to the local pre-amp transistor through a select transistor, the local main-amp transistor connecting to the local pre-amp node for driving the global bit line.
3. The memory device of claim 1 , wherein the first reduced swing amplifier is composed of the local pre amplifier including the local pre-charge transistor for pre-charging the local bit line to the pre-charge voltage, the local pre-amp transistor for detecting whether the local bit line is higher than the pre-charge voltage or not; and the local main amplifier including the local pre-set transistor for pre-setting the local pre-amp node connecting to the local pre-amp transistor, the local main-amp transistor connecting to the local pre-amp node for driving the global bit line.
4. The memory device of claim 1 , wherein the first reduced swing amplifier is reversely configured in polarity for limiting voltage swing from ground voltage to the pre-determined voltage, such that the first reduced swing amplifier is composed of the local pre amplifier including the local pre-charge transistor for pre-charging the local bit line to the predetermined voltage, the local pre-amp transistor for detecting whether the local bit line is lower than the pre-determined or not; and the local main amplifier including the local pre-set transistor for pre-setting the local pre-amp node connecting to the local pre-amp transistor through a pre-amp select transistor, the local main-amp transistor connecting to the local pre-amp node for driving the global bit line; and the second reduced swing amplifier is reversely configured.
5. The memory device of claim 1 , wherein the local pre-amp transistor and the local main-amp transistor are composed of longer channel length transistor than that of the local pre-charge transistor and the pre-set transistor, for reducing power consumption.
6. The memory device of claim 1 , wherein the local pre-amp transistor and the local main-amp transistor are composed of low threshold MOS transistor, for realizing high speed operation.
7. The memory device of claim 1 , wherein the write transistor is composed of a MOS transistor, such as an NMOS transistor and a PMOS transistor.
8. The memory device of claim 1 , wherein the global sense amp includes the global read circuit, the global write circuit, the global latch circuit, the data transfer circuit and the data receive circuit, such that the global read circuit is composed of the global pre amplifier and the global main amplifier, the global latch circuit includes a cross coupled inverter latch and a latch reset transistor, the global write circuit includes a reduced swing inverter and a write drive transistor, the data transfer circuit includes a read selector, a bypass tri-state inverter, a common reset transistor and a read inverter, and the data receive circuit includes a receive control circuit and a receive switch.
9. The memory device of claim 1 , wherein the global sense amp includes the global read circuit, the global latch circuit, the global write circuit, the data transfer circuit and the data receive circuit, such that the global read circuit is composed of the global pre amplifier and the global main amplifier, the global latch circuit includes a cross coupled inverter latch and a latch reset transistor, the global write circuit includes a reduced swing inverter and a write drive transistor, the data transfer circuit includes a read selector, a bypass tri-state inverter, a common reset transistor and a read inverter, and the data receive circuit is composed of a receive NAND gate, a receive inverter and a receive tri-state inverter.
10. The memory device of claim 1 , wherein the pre-charge voltage is set around 0.5V.
11. The memory device of claim 1 , wherein the locking signal generator includes a tunable delay circuit which receives an output from the global latch circuit, where tuning information for the tunable delay circuit is stored in a nonvolatile memory.
12. The memory device of claim 1 , wherein the pass transistor of the memory cell is composed of a MOS transistor, such as an NMOS transistor and a PMOS transistor.
13. The memory device of claim 1 , wherein the pass transistor of the memory cell is formed from various materials, such as single crystalline silicon, poly crystalline silicon, silicon-germanium and germanium.
14. The memory device of claim 1 , wherein the capacitor of the memory cell is composed of a MOS capacitor.
15. The memory device of claim 1 , wherein the capacitor of the memory cell is composed of multiple plates for configuring a finger-like capacitor.
16. The memory device of claim 1 , wherein the capacitor of the memory cell is composed of multiple capacitors, such that a first fingered shape capacitor is formed in between a first routing layer and a second routing layer, and a second fingered shape capacitor is formed in between the second routing layer and a third routing layer.
17. The memory device of claim 1 , wherein the capacitor of the memory cell is composed of a cup-like capacitor.
18. The memory device of claim 1 , wherein the capacitor of the memory cell is formed from various dielectric materials, such as silicon dioxide, silicon nitride, Ta2O5, TiO2, Al2O3, TiN/HfO2/TiN(TIT), and Ru/Insulator/TiN(RIT).
19. The memory device of claim 1 , wherein the memory cell is stacked over peripheral circuits.
20. The memory device of claim 1 , wherein the memory cell is stacked over another memory cell.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 22, 2008
June 23, 2009
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