An output driver capable of controlling a short circuit current includes a driving unit and a driving control unit. The driving unit receives a first driving signal and a second driving signal in response to a control signal and generates an output signal. The driving unit control unit includes a driving unit copying unit having the same construction as the driving unit and compares an output copying signal generated from the first and second driving signals by the driving unit copying unit with a reference voltage and generates the control signal that controls delays of the first and second driving signals in a test mode.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An output driver comprising: a driving unit receiving a first driving signal and a second driving signal and generating an output signal; and a driving control unit including a driving unit copying unit that is identical to the driving unit, the driving control unit comparing an output copying signal generated from the first driving signal and the second driving signal by the driving unit copying unit with a reference voltage and generating a control signal that controls delays applied to the first and second driving signals in a test mode, wherein the driving unit includes a first delay controller delaying the first driving signal in response to the control signal, and a second delay controller delaying the second driving signal in response to the control signal.
2. The output driver of claim 1 , wherein the driving unit comprises: a first inverter receiving the first driving signal; a second inverter receiving the second driving signal; a PMOS transistor having a source connected to a power supply voltage, a gate connected to an output of the first inverter, and a drain connected to a mode for the output signal; and an NMOS transistor having a source connected to a ground voltage, a gate connected to an output of the second inverter, and a drain connected to the mode for the output signal
3. The output driver of claim 1 , wherein the driving control unit comprises: the driving unit copying unit receiving the first and second driving signals and generating the output copying signal in response to the first and second driving signals; a reference voltage generation unit generating the reference voltage from a power supply voltage; and a comparison unit comparing the output copying signal with the reference voltage and generating the control signal.
4. The output driver of claim 3 , wherein the driving unit copying unit comprises: a first inverter receiving the first driving signal; a second inverter receiving the second driving signal; a PMOS transistor having a source connected to the output copying signal and a gate connected to an output of the first inverter; an NMOS transistor having a source connected to a ground voltage, a gate connected to an output of the second inverter, and a drain connected to a drain of the PMOS transistor; a first delay controller delaying the first driving signal in response to the control signal; and a second delay controller delaying the second driving signal in response to the control signal.
5. The output driver of claim 3 , wherein the reference voltage generation unit comprises: a first resistor connected between the power supply voltage and the reference voltage; a second resistor having one end connected to the first resistor; and an NMOS transistor having a drain connected to the other end of the second resistor, a source connected to the ground voltage, and a gate connected to an enable signal.
6. An output driver comprising: a driving unit receiving a first driving signal and a second driving signal and generating an output signal in response to the first and second driving signals; a driving unit copying unit receiving the first driving signal and the second driving signal and generating an output copying signal and a ground copying signal in response to the first and second driving signals; a copying unit precharge unit providing a power supply voltage as the output copying signal; a copying unit enable unit providing a ground voltage as the ground copying signal; a reference voltage generation unit generating a reference voltage from the power supply voltage and the ground voltage; and a comparison unit comparing the output copying signal with the reference voltage and generating a control signal that controls delays applied to the first driving signal and the second driving signal fed to the driving unit and the driving copying unit.
7. The output driver of claim 6 , wherein the driving unit comprises: a first inverter receiving the first driving signal; a second inverter receiving the second driving signal; a PMOS transistor having a source connected to the power supply voltage, a gate connected to an output of the first inverter, and a drain connected to a mode for the output signal; an NMOS transistor having a source connected to the ground voltage, a gate connected to an output of the second inverter, and a drain connected to the output signal; a first delay controller delaying the first driving signal in response to the control signal; and a second delay controller delaying the second driving signal in response to the control signal.
8. The output driver of claim 7 , wherein each of the first and second delay controllers is made up of delay units having different delay times.
9. The output driver of claim 6 , wherein the driving unit copying unit comprises: a first inverter receiving the first driving signal; a second inverter receiving the second driving signal; a PMOS transistor having a source connected to the copying unit precharge unit and a gate connected to an output of the first inverter; an NMOS transistor having a source connected to the copying unit enable unit, a gate connected to an output of the second inverter, and a drain connected to a drain of the PMOS transistor; a first delay controller delaying the first driving signal in response to the control signal; and a second delay controller delaying the second driving signal in response to the control signal.
10. The output driver of claim 9 , wherein each of the first and second delay controllers is made up of delay units having different delay times.
11. The output driver of claim 6 , wherein the copying unit precharge unit is made up of a PMOS transistor that is connected between the power supply voltage and the output copying signal and has a gate connected to a precharge signal.
12. The output driver of claim 6 , wherein the copying unit enable unit is made up of an NMOS transistor that is connected between the ground copying signal and the ground voltage and has a gate connected to an enable signal.
13. The output driver of claim 6 , wherein the reference voltage generation unit comprises: a first resistor connected between the power supply voltage and the reference voltage; a second resistor having one end connected to the first resistor; and an NMOS transistor having a drain connected to the other end of the second resistor, a source connected to the ground voltage, and a gate connected to an enable signal.
14. The output driver of claim 13 , wherein the driving unit copying unit comprises: a first inverter receiving the first driving signal; a second inverter receiving the second driving signal; a PMOS transistor having a source connected to the copying unit precharge unit and a gate connected to an output of the first inverter; an NMOS transistor having a source connected to the copying unit enable unit, a gate connected to an output of the second inverter, and a drain connected to a drain of the PMOS transistor; a first delay controller delaying the first driving signal in response to the delay control signal received via the first switching terminal; and a second delay controller delaying the second driving signal in response to the delay control signal received via the second switching terminal.
15. The output driver of claim 14 , wherein each of the first and second delay controllers is made up of delay units having identical delay times.
16. The output driver of claim 14 , wherein each of the first and second delay controllers is made up of delay units having different delay times.
17. An output driver comprising: a switching unit transmitting a delay control signal to a first switching terminal or a second switching terminal in response to a control signal; a driving unit receiving a first driving signal and a second driving signal in response to the delay control signal received via the first switching terminal or the second switching terminal and generating an output signal in response to the first driving signal and the second driving signal; a driving unit copying unit receiving the first driving signal and the second driving signal in response to the delay control signal received via the first switching terminal or the second switching terminal and generating an output copying signal and a ground copying signal in response to the first and second driving signals; a copying unit precharge unit providing a power supply voltage as the output copying signal; a copying unit enable unit providing a ground voltage as the ground copying signal; a reference voltage generation unit generating a reference voltage from the power supply voltage and the ground voltage; and a comparison unit comparing the output copying signal with the reference voltage and generating the delay control signal.
18. The output driver of claim 17 , wherein the driving unit comprises: a first inverter receiving the first driving signal; a second inverter receiving the second driving signal; a PMOS transistor having a source connected to the power supply voltage, a gate connected to an output of the first inverter, and a drain connected to a node for the output signal; an NMOS transistor having a source connected to the ground voltage, a gate connected to an output of the second inverter, and a drain connected to the node for the output signal; a first delay controller delaying the first driving signal in response to the delay control signal received via the first switching terminal; and a second delay controller delaying the second driving signal in response to the delay control signal received via the second switching terminal.
19. The output driver of claim 18 , wherein each of the first and second delay controllers is made up of delay units having identical delay times.
20. The output driver of claim 18 , wherein each of the first and second delay controllers is made up of delay units having different delay times.
21. An output diver comprising: a driving unit receiving a first diving signal and a second diving signal in response to a plurality of counter bit signals and generating an output signal based on the first and second driving signals; a driving unit copying unit receiving the first driving signal and the second driving signal in response to the counter bit signals and outputting an output copying signal and a ground copying signal; a copying unit precharge unit providing a power supply voltage as the output copying signal; a copying unit enable unit providing a ground voltage as the ground copying signal; a reference voltage generation unit generating a reference voltage from the power supply voltage and the ground voltage; a comparison unit comparing the output copying signal with the reference voltage and generating a control signal; and a counter generating the counter bit signals in response to the control signal, the counter bit signals being up counted or down counted.
22. The output driver of claim 21 , wherein the driving unit comprises: a first inverter receiving the first driving signal; a second inverter receiving the second driving signal; a PMOS transistor having a source connected to the power supply voltage, a gate connected to an output of the first inverter, and a drain connected to a node for the output signal; an NMOS transistor having a source connected to the ground voltage, a gate connected to an output of the second inverter, and a drain connected to the node for the output signal; a first delay controller delaying the first driving signal in response to the counter bit signals; and a second delay controller delaying the second driving signal in response to the counter bit signals.
23. The output driver of claim 22 , wherein each of the first and second delay controllers is made up of capacitors that are implemented as transistors connected between each of the counter bit signals and the first or second driving signal.
24. The output driver of claim 21 , wherein the driving unit copying unit comprises: a first inverter receiving the first driving signal; a second inverter receiving the second driving signal; a PMOS transistor having a source connected to the copying unit precharge unit and a gate connected to an output of the first inverter; an NMOS transistor having a source connected to the copying unit enable unit, a gate connected to an output of the second inverter, and a drain connected to a drain of the PMOS transistor; a first delay controller delaying the first driving signal in response to the counter bit signals; and a second delay controller delaying the second driving signal in response to the counter bit signals.
25. The output driver of claim 24 , wherein each of the first and second delay controllers is made up of capacitors that are implemented as transistors connected between each of the counter bit signals and the first or second driving signal.
26. An output driver comprising: a switching unit transmitting a plurality of counter bit signals to a first switching terminal or a second switching terminal in response to a control signal; a driving unit receiving a first driving signal and a second driving signal in response to the counter bit signals received via the first switching terminal or the second switching terminal and generating an output signal based on the first and second driving signals; a driving unit copying unit receiving the first and second driving signals in response to the counter hit signals received via the first switching terminal or the second switching terminal and generating an output copying signal and a ground copying signal based on the first and second driving signals; a copying unit precharge unit providing a power supply voltage as the output copying signal; a copying unit enable unit providing a ground voltage as the ground copying signal; a reference voltage generation unit generating a reference voltage from the power supply voltage and the ground voltage; a comparison unit comparing the output copying signal with the reference voltage and generating a control signal; and a counter generating the counter bit signals in response to the control signal, the counter bit signals being up counted or down counted.
27. The output driver of claim 26 , wherein the driving unit comprises: a first inverter receiving the first driving signal; a second inverter receiving the second driving signal; a PMOS transistor having a source connected to the power supply voltage, a gate connected to an output of the first inverter, and a drain connected to a node for the output signal; an NMOS transistor having a source connected to the ground voltage, a gate connected to an output of the second inverter, and a drain connected to the node for the output signal; a first delay controller delaying the first driving signal in response to the counter bit signals; and a second delay controller delaying the second driving signal in response to the counter bit signals.
28. The output driver of claim 27 , wherein each of the first and second delay controllers is made up of capacitors that are implemented as transistors connected between each of the counter bit signals and the first or second driving signal.
29. The output driver of claim 26 , wherein the driving unit copying unit comprises: a first inverter receiving the first driving signal; a second inverter receiving the second driving signal; a PMOS transistor having a source connected to the copying unit precharge unit and a gate connected to an output of the first inverter; an NMOS transistor having a source connected to the copying unit enable unit, a gate connected to an output of the second inverter, and a drain connected to a drain of the PMOS transistor; a first delay controller delaying the first driving signal in response to the counter bit signals; and a second delay controller delaying the second driving signal in response to the counter bit signals.
30. The output driver of claim 29 , wherein each of the first and second delay controllers is made up of capacitors that are implemented as transistors connected between each of the counter bit signals and the first or second driving signal.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 12, 2006
July 14, 2009
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