Methods and apparatus are provided for decoupling a cryptography accelerator interface from cryptographic processing cores. A shared resource is provided at the cryptography accelerator interface having multiple input ports. References to data in the shared resource are provided to allow processing and ordering of data in preparation for processing by cryptographic processing cores without substantial numbers of separate buffers in the cryptographic processing data paths.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A cryptography accelerator, comprising: a plurality of input ports configured to receive data comprising header information and data blocks; a plurality of cryptographic processing cores, each cryptographic processing core having a plurality of data paths; an input buffer coupled to the plurality of input ports and cryptographic processing cores, wherein the input buffer is shared by the plurality of input ports and the plurality of data paths associated with each cryptographic processing core in the plurality of cryptographic processing cores; an input controller coupled to the plurality of input ports, wherein the input controller dynamically allocates resources of the input buffer to the plurality of input ports and to the plurality of data paths associated with each cryptographic processing core in the plurality of cryptographic processing cores; and wherein the shared input buffer is dynamically allocable by varying a number of entries in a buffer pointer table allocated to each of the plurality of ports.
2. The cryptography accelerator of claim 1 , wherein policy and security association information is extracted based on source and destination addresses and source and destination ports of the data blocks.
3. The cryptography accelerator of claim 1 , wherein policy and security association information comprises key and algorithm information.
4. The cryptography accelerator of claim 1 , wherein the plurality of input ports comprise a streaming interface port.
5. The cryptography accelerator of claim 4 , wherein the plurality of input ports further comprise a memory mapped port.
6. The cryptography accelerator of claim 1 , wherein the buffer pointer table comprises a plurality of pointers.
7. The cryptographic accelerator of claim 1 , further comprising: policy security association lookup circuitry configured to receive header information and determine policy and security association information associated with the data blocks, wherein the policy and security association information is forwarded with the data blocks to cryptographic processing cores.
8. The cryptography accelerator of claim 7 , wherein the policy security association lookup circuitry receives a pointer to header information.
9. A cryptography accelerator comprising: a plurality of input ports configured to receive data comprising header information and data blocks; a plurality of cryptographic processing cores; an input buffer coupled to the plurality of input ports and cryptographic processing cores, wherein the input buffer is shared by the plurality of input ports and the plurality of cryptographic processing cores; an input controller coupled to the plurality of input ports, wherein the input controller dynamically allocates resources of the input buffer to the plurality of input ports and the plurality of cryptographic processing cores; and a buffer pointer table associated with the plurality of input ports, the buffer pointer table having a plurality of entries configured to hold header information from the plurality of input ports, the plurality of entries referencing data blocks in the shared input buffer.
10. The cryptography accelerator of claim 9 , further comprising: a data input unit load distributor configured to select entries from the buffer pointer table.
11. The cryptography accelerator of claim 10 , further comprising: an output controller configured to receive buffer pointer table entries from the load distributor, pull data blocks corresponding to the entries from the input buffer, and forward the data blocks to a plurality of data paths associated with the plurality of cryptographic processing cores.
12. The cryptography accelerator of claim 11 , further comprising a merge data unit coupled to the output controller and the policy security association lookup circuitry, wherein the merge data unit is configured to wait for the policy and security association information and the corresponding data block before forwarding the policy and security association information along with the data block to a cryptographic processing core.
13. The cryptographic accelerator of claim 7 , wherein the input controller is configured to write data blocks from the plurality of input ports into the input buffer and write entries corresponding to the data blocks into the buffer pointer table.
14. A method for data handling in a cryptography accelerator having a plurality of input ports and a plurality of cryptographic processing cores, comprising: each cryptographic processing core having a plurality of data paths; receiving data at the plurality of input ports; dynamically allocating space in an input buffer shared by the plurality of input ports and the plurality of data paths associated with each cryptographic processing core in the plurality of cryptographic processing cores to the received data; and allocating space in the shared input buffer to data used by the a data path associated a cryptographic processing core to process the received data; and wherein the input buffer is dynamically allocated by varying the number of entries in a buffer pointer table allocated to each of the plurality of input ports.
15. The method of claim 14 , wherein the shared resource is a buffer shared by the plurality of input ports.
16. The method of claim 14 , wherein the references are pointers to entries in the shared resource.
17. The method of claim 16 , wherein the references are included in a buffer pointer table.
18. The method of claim 17 , wherein the shared resource can be allocated based on needs of particular input ports.
19. A method for data handling in a cryptography accelerator having a plurality of input ports and a plurality of cryptographic processing cores comprising: receiving data at the plurality of input ports; dynamically allocating space in an input buffer shared by the plurality of input ports and the plurality of cryptographic processing cores to the received data; allocating space in the shared input buffer to data used by the cryptographic processing core to process the received data; providing references to the received data in the shared input buffer, wherein the references identify the received data as well as the type of the received data; performing a policy security association lookup to determine policy and security association information associated with the received data; and forwarding the received data along with policy and security association to the plurality of cryptographic processing cores.
20. A cryptography accelerator, comprising: a plurality of input ports configured to receive data comprising header information and data blocks; a plurality of cryptographic processing cores, each cryptographic processing core having a plurality of data paths; a bypass line coupling the plurality of input ports to a plurality of output ports; an input buffer coupled to the plurality of input ports and cryptographic processing cores, wherein the input buffer is shared by the plurality of input ports and the plurality of data paths associated with each cryptographic processing core in the plurality of cryptographic processing cores; an input controller coupled to the plurality of input ports, wherein the input controller dynamically allocates resources of the input buffer to the plurality of input ports and to the plurality of data paths associated with each cryptographic processing core in the plurality of cryptographic processing cores; and a target list having a bypass list associated with data blocks to be passed through the cryptography accelerator without cryptographic processing.
21. A cryptography accelerator, comprising: a plurality of input ports configured to receive data comprising header information and data blocks; a plurality of cryptographic processing cores; a bypass line coupling the plurality of input ports to a plurality of output ports; an input buffer coupled to the plurality of input ports and cryptographic processing cores, wherein the input buffer is shared by the plurality of input ports and the plurality of cryptographic processing cores and wherein the input buffer is dynamically allocated by varying the number of entries in a buffer pointer table allocated to each of the plurality of input ports; an input controller coupled to the plurality of input ports, wherein the input controller dynamically allocates resources of the input buffer to the plurality of input ports and the plurality of cryptographic processing cores; and a target list having a bypass list associated with data blocks to be passed through the cryptography accelerator without cryptographic processing.
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January 23, 2003
July 28, 2009
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