Method for producing a buried semiconductor layer

1. A method for producing a power transistor in a semiconductor body, the power transistor including an n-doped substrate, an n-doped semiconductor layer provided on the n- doped substrate, and a p-doped region provided within the upper region of the n-doped semiconductor layer, the method comprising: a) irradiating at least a part of a front side of the semiconductor body with protons, and b) heat treating the semiconductor body at a temperature of approximately between 450 C and 550 C, wherein by the heat treatment a region of increased n-doping is formed in the n-doped semiconductor layer between the n-doped substrate and the p-doped region, which contains proton-induced donors and which includes an essentially homogenous doping profile due to a combination of the irradiated protons with defects caused by irradiation, wherein the homogenous doping profile extends from a doping maximum and in the direction of the front side of the semiconductor body, wherein the region of increased n-doping in the upper region of the n-doped semiconductor layer is immediately adjacent to the p-doped body region.

2. The method according to claim 1 , wherein the n-doped semiconductor layer is generally a layer deposited by means of an epitaxial method.

3. The method as claimed in claim 1 , wherein the irradiating further comprises irradiating the at least one part of a surface, such that the surface comprises a surface of the semiconductor body which is closes to a source contact of the semiconductor body.

4. The method as claimed in claim 1 , further comprising using the region of increased n-doping as at least one part of a drift path of the power transistor.

5. The method as claimed in claim 4 , wherein the irradiating further comprises selecting irradiation parameters such that the resulting drift path is compensatable.

6. The method as claimed in claim 5 , wherein the region of increased n-doping comprises at least 30% of a vertical extent of the drift path.

7. The method as claimed in claim 6 , wherein the region of increased n-doping comprises at least 50% or 70% of the vertical extent of the drift path.

8. The method as claimed in claim 1 , further comprising, after the irradiating step, performing at least one additional proton irradiation with at least one different irradiation parameter prior to the heat-treating step.

9. The method as claimed in claim 8 , wherein performing at least one additional proton irradiation further comprises performing the at least one different proton irradiation on at least a first part of the region of increased n-doping differs from a second part of the region with increased doped irradiated in the irradiation step.

10. The method as claimed in claim 1 , wherein the irradiation step further comprises irradiating at least one part of a surface of the semiconductor body through a screen of defined thickness arranged in front of the semiconductor body.

11. The method as claimed in claim 10 , wherein the screen is configured in such a way that a doping of an edge region of the power transistor is substantially avoided.

12. The method as claimed in claim 1 , wherein the power transistor is a power MOSFET.

13. A process for jointly fabricating power transistors with a compensation structure and further semiconductor components without compensation structure in a common n-doped semiconductor layer wherein the regions with increased n-doping, of the n-doped semiconductor layer within the power transistor with compensation structure is produced according to the method of claim 1 .