Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments allows feedback timing to be adjusted independent of the sample timing to measure the effects of some forms of phase misalignment and jitter.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A receive circuit comprising: a. a data input terminal to receive a stream of input data symbols; b. a first data sampler having a first data input port, a first data output port, and a first clock terminal to receive a first clock signal, the first data sampler to sample the input data symbols responsive to the first clock signal; c. a second data sampler having a second data input port, a second data output port, and a second clock terminal to receive a second clock signal, the second data sampler to sample the input data symbols responsive to the second clock signal; d. an expected-data source different from the second data output port to provide a stream of expected values representative of historical ones of the input data symbols; e. a decision feedback path extending from the expected-data source to the second data input port, the feedback path to produce a weighted sum of the stream of expected values; and f. clocking circuitry to provide the second clock signal to the second clock terminal at a different phase than the first clock signal.
2. The receive circuit of claim 1 , wherein the first data sampler is a dedicated data sampler, the second data sampler is a dedicated roving data sampler, and the clocking circuitry is adapted to dynamically vary the phase of the second clock signal.
3. The receive circuit of claim 1 , wherein the expected-data source receives the expected values representative of historical ones of the input data symbols from the first data output port.
4. The receive circuit of claim 1 , further comprising a comparison circuit having a first comparison-circuit input node coupled to the first data output port, a second comparison-circuit input node coupled to the second data output node, and a comparison-circuit output node.
5. A receive circuit comprising: a. a data input terminal to receive a stream of input data symbols; b. a first data sampler having a first data input port, a first data output port, and a first clock terminal to receive a sample clock signal; c. a second data sampler having a second data input port, a second data output port, and a second clock terminal; d. an expected-data source different from the second data output port to provide a stream of expected values representative of historical ones of the input data symbols; e. a decision feedback path extending from the expected-data source to the second data input port, the feedback path to produce a weighted sum of the stream of expected values; and f. a comparison circuit to compare a first stream of sampled data output from the first data sampler with a second stream of sampled data output from the second data sampler, wherein the comparison circuit issues an error signal in response to mismatches between corresponding symbols in the first and second streams.
6. The receive circuit of claim 5 , wherein the comparison circuit issues an error signal in response to each mismatch between the first and second streams.
7. The receive circuit of claim 4 , wherein the comparison circuit includes a sample filter coupled to the comparison-circuit output node to assert an error signal if (a) at least one of the input data symbols sampled responsive to the first clock signal differs from the same input data symbols sampled responsive to the second clock signal and (b) the at least one of the input data symbols sampled responsive to the first clock signal matches the corresponding expected values of the input data.
8. The receive circuit of claim 1 , wherein the second data sampler is a roving data sampler in a margin-test mode and a main sampler in an operational mode, and wherein the decision feedback path extends from the second data output port to the second data input port in the operational mode.
9. The receive circuit of claim 1 , wherein the expected values are constant.
10. The receive circuit of claim 1 , further comprising a second decision feedback path extending from the first data output port to the first data input port.
11. The receive circuit of claim 1 instantiated on a single semiconductor chip.
12. A method of operation within a digital receiver having at a first sampler and a second sampler, comprising: a. receiving a series of input symbols; b. adding a weighted, time-shifted version of the input symbols to the series of input symbols to develop a first series of equalized input symbols; c. sampling with the first sampler the first series of equalized input symbols using a first clock signal, to produce a first series of sampled symbols from a first data output port; d. deriving the weighted, time-shifted version of the input symbols from the first series of sampled symbols; e. adding expected data to the series of input symbols to develop a second series of equalized input symbols wherein the source of the expected data is different from a second data output port; and f. sampling with the second sampler the second series of equalized input symbols using a second clock signal, to produce a second series of sampled symbols from the second data output port.
13. The method of claim 12 , wherein the expected data does not transition with the time-shifted version of the input symbols.
14. The method of claim 12 , wherein the expected data comprises a steady-state value representative of a logic level.
15. The method of claim 12 , wherein the expected data is out of phase with respect to the second clock signal.
16. The method of claim 12 , wherein the expected data is of a lower frequency than the series of input signals.
17. The method of claim 12 , further comprising selecting the first series of sampled signals as the expected data.
18. The method of claim 12 , further comprising comparing the first series of sampled symbols with the second series of sampled symbols and asserting an error signal when the first and second series of sampled symbols fail to match.
19. The method of claim 18 , further comprising asserting the error signal only when the first and second series of sampled symbols fail to match for particular values of the expected data.
20. The method of claim 12 , wherein the weighted, time-shifted version of the input symbols are derived using a first feedback path and the expected data are conveyed via a second feedback path.
21. A receiver comprising: a. a data input terminal to receive a stream of input data symbols; b. a first data sampler having a first data input port, a first data output port, and a first clock terminal to receive a first clock signal of a first phase and sample data responsive to the first clock signal; c. a second data sampler having a second data input port, a second data output port, and a second clock terminal to receive a second clock signal of a second phase different than the first phase and sample data responsive to the second clock signal; d. means for applying weighted, time-shifted expected values representative of prior ones of the input data symbols to the second data input port, wherein the source of the expected values is different from the second data output port.
22. The receiver of claim 21 , wherein the weighted, time-shifted expected values comprise a steady-state value.
23. The receiver of claim 22 , wherein the weighted, time-shifted expected values comprise a voltage level.
24. The receiver of claim 21 , further comprising means for comparing a first output data stream from the first data output port with a second output data stream from the second data output port.
25. The receiver of claim 24 , further comprising a data filter coupled to an output of the means for comparing.
26. The method of claim 12 , wherein the second data sampler is in a margin-test mode when adding the expected data to the series of input signals, the method further comprising, in an operational mode, adding a second weighted, time-shifted version of the input symbols to the series of input symbols to develop a third series of equalized input symbols and sampling the third series of equalized input symbols with the second sampler.
27. The receiver of claim 24 , further comprising: a. means for varying the second phase relative to the first phase; and b. means for comparing a first output data stream from the first data output port with a second output data stream from the second data output port and for detecting mismatch to identify data eye timing margins.
28. A receive circuit comprising: a first equalizer coupled to a data input terminal to receive and equalize a stream of input data symbols; a first data sampler having a first data input port coupled to the first equalizer to receive the equalized stream of input data symbols from the first equalizer, a first data output port, and a first clock terminal to receive a first sample clock signal, the first data sampler to sample the equalized stream of input signals from the first equalizer to produce a first series of data samples; a second equalizer coupled to the data input terminal to receive and equalize the stream of input data symbols; a second data sampler having a second data input port coupled to the second equalizer to receive the equalized stream of input data symbols from the second equalizer, a second data output port, and a second clock terminal to receive a second sample clock signal, the second data sampler to sample the equalized stream of input signals from the second equalizer to produce a second series of data samples; an expected-data source to provide a constant value representative of a subset of historical ones of the input data symbols; and a decision feedback path extending from the expected-data source to the second equalizer, the feedback path to produce a weighted sum of the constant value.
29. The receive circuit of claim 28 , wherein the first sample clock signal has a first phase and the second sample clock signal has a second phase and the first and second phases are independent.
30. The receive circuit of claim 28 , further comprising a comparison circuit having a first comparison-circuit input node coupled to the first data output port, a second comparison-circuit input node coupled to the second data output node, and a comparison-circuit output node.
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April 28, 2006
September 15, 2009
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