An integrated circuit includes a resistance changing memory element and a circuit. The circuit is configured to program the memory element by iteratively applying a variable program pulse to the memory element until a resistance of the memory element crosses a first reference resistance. The variable program pulse is adjusted for each iteration such that the resistance of the memory element approaches the first reference resistance.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit comprising: a resistance changing memory element; and a circuit configured to program the memory element by iteratively applying a reset pulse followed by a variable program pulse to the memory element until a resistance of the memory element crosses a first reference resistance, the variable program pulse adjusted for each iteration such that the resistance of the memory element approaches the first reference resistance, and the reset pulse for each iteration programming the memory element to a substantially amorphous state prior to each variable program pulse.
2. The integrated circuit of claim 1 , wherein the circuit is configured to program the memory element by iteratively applying the reset pulse followed by a variable partial set program pulse to the memory element until the resistance of the memory element is less than the first reference resistance.
3. The integrated circuit of claim 1 , wherein the circuit is configured to program the memory element by iteratively applying the reset pulse followed by a variable partial set program pulse to the memory element until the resistance of the memory element is less than the first reference resistance and greater than a second reference resistance.
4. The integrated circuit of claim 1 , wherein the circuit is configured to program the memory element by iteratively applying the reset pulse followed by a variable partial set program pulse to the memory element until the resistance of the memory element is greater than the first reference resistance.
5. The integrated circuit of claim 1 , wherein the circuit is configured to program the memory element by iteratively applying the reset pulse followed by a variable partial reset program pulse to the memory element until the resistance of the memory element is less than the first reference resistance.
6. The integrated circuit of claim 1 , wherein the circuit is configured to program the memory element by iteratively applying the reset pulse followed by a variable partial reset program pulse to the memory element until the resistance of the memory element is greater than the first reference resistance.
7. The integrated circuit of claim 1 , wherein the circuit comprises a counter configured to count the iterations and terminate programming of the memory element in response to the count reaching a predetermined value.
8. The integrated circuit of claim 1 , wherein the resistance changing memory element comprises a phase change memory element.
9. A system comprising: a host; and a memory device communicatively coupled to the host, the memory device comprising: a phase change memory element; a write circuit configured to program the memory element by iteratively applying a variable program pulse to the memory element until a resistance of the memory element crosses a reference resistance, the variable program pulse adjusted for each iteration such that the resistance of the memory element approaches the reference resistance; and a counter configured to count the iterations and terminate programming of the memory element in response to the count reaching a predetermined value.
10. The system of claim 9 , wherein the write circuit is configured to apply a reset pulse before each variable program pulse.
11. The system of claim 10 , wherein the write circuit is configured to program the memoiy element by iteratively applying a variable partial set pulse to the memory element until the resistance of the memory element is less than the reference resistance.
12. The system of claim 10 , wherein the write circuit is configured to program the memory element by iteratively applying a variable partial set pulse to the memory element until the resistance of the memory element is greater than the reference resistance.
13. The system of claim 10 , wherein the write circuit is configured to program the memory element by iteratively applying a variable partial reset pulse to the memory element until the resistance of the memory element is less than the reference resistance.
14. The system of claim 10 , wherein the write circuit is configured to program the memory element by iteratively applying a variable partial reset pulse to the memory element until the resistance of the memory element is greater than the reference resistance.
15. The system of claim 9 , wherein the memory device further comprises: a sense circuit configured to read the resistance of the memory element; and a controller configured to control the write circuit and the sense circuit.
16. A method for programming a memory element, the method comprising: iteratively applying a reset pulse to the memory element to program the memory element to a substantially amorphous state followed by applying a variable program pulse to the memory element, reading a resistance of the memory element, and comparing the read resistance to a reference resistance until the read resistance crosses the reference resistance; and adjusting the variable program pulse for each iteration such that the resistance of the memory element approaches the reference resistance.
17. The method of claim 16 , wherein iteratively applying the reset pulse followed by the variable program pulse to the memory element, reading the resistance of the memory element, and comparing the read resistance to the reference resistance comprises iteratively applying the reset pulse followed by a variable partial set program pulse to the memory element, reading the resistance of the memory element, and comparing the read resistance to the reference resistance until the read resistance is less than the reference resistance.
18. The method of claim 16 , wherein iteratively applying the reset pulse followed by the variable program pulse to the memory element, reading the resistance of the memory element, and comparing the read resistance to the reference resistance comprises iteratively applying the reset pulse followed by a variable partial set program pulse to the memory element, reading the resistance of the memory element, and comparing the read resistance to the reference resistance until the read resistance is greater than the reference resistance.
19. The method of claim 16 , wherein iteratively applying the reset pulse followed by the variable program pulse to the memory element, reading the resistance of the memory element, and comparing the read resistance to the reference resistance comprises iteratively applying the reset pulse followed by a variable partial reset program pulse to the memory element, reading the resistance of the memory element, and comparing the read resistance to the reference resistance until the read resistance is less titan the reference resistance.
20. The method of claim 16 , wherein iteratively applying the reset pulse followed by the variable program pulse to the memory element, reading the resistance of the memory element, and comparing the read resistance to the reference resistance comprises iteratively applying the reset pulse followed by a variable partial reset program pulse to the memory element, reading the resistance of the memory element, and comparing the read resistance to the reference resistance until the read resistance is greater than the reference resistance.
21. The method of claim 16 , further comprising: counting the number of iterations; and terminating the iterations in response to a count of the counter reaching a predetermined value.
22. The method of claim 16 , wherein iteratively applying the program pulse comprises iteratively applying the program pulse to a phase change memory element.
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December 7, 2007
September 22, 2009
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