A multiport memory 2 is provided with control circuitry 14 which detects signal values indicative of concurrent write and read accesses via respective bit lines of a plurality of data access ports to a common row of bit cells. When such signals are detected, an override signal is generated and supplied to override circuitry 34, 36, 38, 40, 42, 44. The override circuitry is responsive to the override signal to drive one or more bit values being written to respective bit cells via their associated bit lines onto associated bit lines of other of a plurality of data access supports that are concurrently enabled for access to their bit cells. Thus, write data is also written onto the bit lines associated with a port performing a concurrent read operation.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A multiport memory comprising: at least one array of bit cells having a plurality of bit lines each coupled to a column of bit cells within said array and a plurality of row lines each coupled to a row of bit cells within said array; a plurality of data access ports coupled to said at least one array of bit cells, each data access port having at least one associated bit line providing data access to a respective column of bits cells within said array such that a given bit cell is enabled for access via said at least one associated bit line when a row line coupled to said given bit cell supplies an access enable signal to a row of bit cells including said given bit cell; control circuitry responsive to signal values indicative of concurrent data accesses via respective associated bit lines of a plurality of data access ports to a common row of bit cells when at least one of said data accesses is a write access via a given data access port to generate an override signal; and override circuitry responsive to said override signal to drive one or more bit values being written to respective bit cells via respective associated bit lines of said given data access port on to associated bit lines of other of said plurality of data access ports that are concurrently enabled for access to said respective bit cells.
2. A multiport memory as claimed in claim 1 , wherein said signals indicative of concurrent data accesses include matching row address signals associated with said plurality of data access ports.
3. A multiport memory as claimed in claim 1 , wherein said signals indicative of concurrent data accesses include write access selecting signals associated with said plurality of data access ports.
4. A multiport memory as claimed in claim 1 , wherein said signals indicative of concurrent data accesses include access clocking signals associated with said plurality of data access ports.
5. A multiport memory as claimed in claim 1 , wherein said signals indicative of concurrent data accesses comprise concurrent matching row address signals associated with said plurality of data access ports, at least one write access selecting signal associated with said plurality of data access ports and concurrent access clocking signals associated with said plurality of data access ports.
6. A multiport memory as claimed in claim 1 , comprising write driver circuitry within said given data access port to drive said one or more bit values and said override circuitry comprises circuitry to couple associated bit lines of said other of said plurality of access ports to said write driver circuitry in response to said override signal.
7. A multiport memory as claimed in claim 1 , wherein said plurality of data access ports comprises one dedicated write access port and one dedicated read access port.
8. A multiport memory as claimed in claim 1 , wherein said plurality of data access ports comprises two access ports each capable of providing both write access and read access.
9. A multiport memory as claimed in claim 1 , wherein said multiport memory is formed of components with less than a 90 nm process size.
10. A multiport memory comprising: at least one array of bit cell means having a plurality of bit lines each coupled to a column of bit cell means within said array and a plurality of row lines each coupled to a row of bit cells within said array; a plurality of data access ports coupled to said at least one array of bit cell means, each data access port having at least one associated bit line providing data access to a respective column of bits cell means within said array such that a given bit cell means is enabled for access via said at least one associated bit line when a row line coupled to said given bit cell means supplies an access enable signal to a row of bit cells including said given bit cell means; control means responsive to signal values indicative of concurrent data accesses via respective associated bit lines of a plurality of data access ports to a common row of bit cells when at least one of said data accesses is a write access via a given data access port for generating an override signal; and override means responsive to said override signal for driving one or more bit values being written to respective bit cells via respective associated bit lines of said given data access port on to associated bit lines of other of said plurality of data access ports that are concurrently enabled for access to said respective bit cells.
11. A method of operating a multiport memory having: at least one array of bit cells having a plurality of bit lines each coupled to a column of bit cells within said array and a plurality of row lines each coupled to a row of bit cells within said array; and a plurality of data access ports coupled to said at least one array of bit cells, each data access port having at least one associated bit line providing data access to a respective column of bits cells within said array such that a given bit cell is enabled for access via said at least one associated bit line when a row line coupled to said given bit cell supplies an access enable signal to a row of bit cells including said given bit cell; said method comprising: in response to signal values indicative of concurrent data accesses via respective associated bit lines of a plurality of data access ports to a common row of bit cells when at least one of said data accesses is a write access via a given data access port, generating an override signal; and in response to said override signal, driving one or more bit values being written to respective bit cells via respective associated bit lines of said given data access port on to associated bit lines of other of said plurality of data access ports that are concurrently enabled for access to said respective bit cells.
12. A method as claimed in claim 11 , wherein said signals indicative of concurrent data accesses include matching row address signals associated with said plurality of data access ports.
13. A method as claimed in claim 11 , wherein said signals indicative of concurrent data accesses include write access selecting signals associated with said plurality of data access ports.
14. A method as claimed in claim 11 , wherein said signals indicative of concurrent data accesses include access clocking signals associated with said plurality of data access ports.
15. A multiport memory as claimed in claim 11 , wherein said signals indicative of concurrent data accesses comprise concurrent matching row address signals associated with said plurality of data access ports, at least one write access selecting signal associated with said plurality of data access ports and concurrent access clocking signals associated with said plurality of data access ports.
16. A method as claimed in claim 11 , comprising, in response to said override signal, coupling associated bit lines of said other of said plurality of access ports to write driver circuitry within said given data access port driving said one or more bit values.
17. A method as claimed in claim 11 , wherein said plurality of data access ports comprises one dedicated write access port and one dedicated read access port.
18. A method as claimed in claim 11 , wherein said plurality of data access ports comprises two access ports each capable of providing both write access and read access.
19. A method as claimed in claim 11 , wherein said multiport memory is formed of components with less than a 90 nm process size.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 16, 2007
October 20, 2009
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