Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal without intervention from a central processing unit (CPU). The resetting may occur via a virtual CPU. Another aspect of the invention may have the signal generation and EEPROM resetting occurring via a virtual CPU integrated within a finite state machine. A frequency counter may be utilized to generate a clock signal from a clock source having a higher frequency than that required by the EEPROM.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for controlling an electrically erasable programmable read only memory (EEPROM), the method comprising: generating a clock signal at a frequency suitable for operation of said EEPROM; and resetting said EEPROM via said generated clock signal and a hardware generated data signal without intervention from a central processing unit (CPU).
2. The method according to claim 1 , wherein said resetting occurs via a virtual CPU.
3. The method according to claim 2 , wherein said virtual CPU is integrated within a finite state machine.
4. The method according to claim 1 , wherein said generating is controlled via a virtual CPU.
5. The method according to claim 1 , wherein said generating is controlled via a finite state machine.
6. The method according to claim 1 , wherein said resetting occurs via a finite state machine.
7. The method according to claim 1 , wherein said generating of said clock signal occurs utilizing a frequency counter.
8. The method according to claim 7 , wherein said frequency counter detects a signal frequency from a clock source having a higher frequency.
9. A system for controlling an EEPROM, the system comprising: one or more circuits for generating a clock signal suitable for operation of said EEPROM; and said one or more circuits resets said EEPROM via said generated clock signal and a hardware generated data signal, without intervention from a central processing unit (CPU).
10. The system according to claim 9 , wherein said one or more circuits comprise a virtual central processing unit (VCPU), which is utilized for said resetting of said EEPROM.
11. The system according to claim 10 , wherein said virtual CPU is integrated within a finite state machine.
12. The system according to claim 9 , wherein said one or more circuits comprises a virtual CPU which controls said generation of said clock signal.
13. The system according to claim 9 , wherein said one or more circuits comprises a finite state machine that controls said generation of said clock signal.
14. The system according to claim 9 , wherein said one or more circuits comprises a finite state machine that controls said resetting of said EEPROM.
15. The system according to claim 9 , wherein said one or more circuits comprises a frequency counter that is utilized for said generation of said clock signal.
16. The system according to claim 15 , wherein said frequency counter detects a signal frequency from a clock source having a higher frequency.
17. A machine-readable storage having stored thereon, a computer program having at least one code section for resetting an EEPROM, the at least one code section being executable by a machine for causing the machine to perform steps comprising: generating a clock signal suitable for operation of said EEPROM; and resetting said EEPROM via said generated clock signal and a hardware generated data signal without intervention from a central processing unit (CPU).
18. The machine-readable storage according to claim 17 , wherein said at least one code section comprises code for generating a reset condition utilizing a virtual central processing unit (VCPU).
19. The machine-readable storage according to claim 18 , wherein said at least one code section comprises code for integrating said virtual CPU within a finite state machine.
20. The machine-readable storage according to claim 17 , wherein said at least one code section comprises code for controlling said generating via a virtual CPU.
21. The machine-readable storage according to claim 17 , wherein said at least one code section comprises code for said resetting occurs via a finite state machine.
22. The machine-readable storage according to claim 17 , wherein said at least one code section comprises code for generating said clock signal utilizing a frequency counter.
23. The machine-readable storage according to claim 17 , wherein said at least one code section comprises code for detecting a signal frequency from a clock source having a higher frequency.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 9, 2007
October 27, 2009
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