An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the placement guide; aligning the placement guide to an integrated circuit chip position on the module substrate; fixing the placement guide to the module substrate; placing an integrated circuit chip in the guide opening, sidewalls of the placement guide opening constraining electrically conductive bonding structures on bottom surface of the integrated circuit chip to self-align to an electrically conductive module substrate contact pad on the top surface of the module substrate in the integrated circuit chip position; and bonding the bonding structures to the module substrate contact pads, the bonding structures and the module substrate contact pads in direct physical and electrical contact after the bonding.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of fabricating an electronic device, comprising: Placing a placement guide over a top surface of a module substrate, a bottom surface of said placement guide facing a top surface of said module substrate, said placement guide having one or more guide openings, said guide openings extending from a top surface of said placement guide to said bottom surface of said placement guide; aligning said placement guide to at least one integrated circuit chip position of one or more integrated circuit chip positions on said module substrate; fixing said aligned placement guide to said module substrate; placing one or more integrated circuit chips in corresponding guide openings of said one or more guide openings, bottom surfaces of said one or more integrated circuit chips facing said top surface of said module substrate, each integrated circuit chip of said one or more integrated circuit chips having first distances between sidewalls of said placement guide openings and corresponding sidewalls of each integrated circuit chip of said one or more integrated circuit chips, said first distances constraining electrically conductive bonding structures on bottom surfaces of each integrated circuit chip of said one or more integrated circuit chips to contact corresponding electrically conductive module substrate contact pads on said top surface of said module substrate; bonding said bonding structures to said module substrate contact pads, said bonding structures and said module substrate contact pads in direct physical and electrical contact after said bonding; and wherein a distance between at least one sidewall of each of said one or more placement guide openings and at least one opposing sidewall of corresponding placed integrated circuit chips is equal to less than one half a distance between centers of a pair of adjacent module substrate contact pads of said module substrate contact pads at each of said corresponding integrated circuit chip positions.
2. The method of claim 1 , further including: after said bonding, removing said placement guide from said module substrate.
3. The method of claim 2 , further including: singulating said module substrate into individual modules, each module substrate containing one or more integrated circuit chips.
4. The method of claim 1 , wherein said bonding structures are solder bumps on chip contact pads and said bonding creates a soldered connection between said chip contact pads and said module substrate contact pads.
5. The method of claim 1 , wherein said bonding structures comprise copper chip contact pads, said module substrate contact pads comprise copper and said bonding creates a copper to copper weld between said chip contact pads and said module substrate contact pads.
6. The method of claim 1 , wherein said placement guide comprises silicon, said integrated circuit chip comprises silicon, and said module substrate comprises silicon.
7. The method of claim 1 , further including: attaching a handle substrate to a bottom surface of said module substrate.
8. The method of claim 1 , wherein corresponding center to center spacing of adjacent module substrate contact pads of at least two of said one or more integrated circuit chip positions is different.
9. The method of claim 1 , wherein said integrated circuit chip is placed on said module substrate after said aligning and fixing said placement guide to said module substrate.
10. The method of claim 1 , wherein said placing said integrated circuit chip on said module substrate is performed before said aligning and fixing said placement guide to said module substrate.
11. The method of claim 1 , further including: after said bonding, removing said placement guide from said module substrate; and after said removing said placement guide, singulating said module substrate into individual modules, each module containing one or more integrated circuit chips.
12. The method of claim 1 , further including: singulating said module substrate into individual modules, each module substrate containing one or more integrated circuit chips.
13. The method of claim 1 , wherein at least one of said one or more integrated circuit chips includes an additional integrated circuit chip stacked on top of and electrically connected to said at least one of said one or more integrated circuit chips.
14. The method of claim 1 , wherein first distances from said top surface of said module substrate to respective top surfaces of each integrated circuit chip of said one or more integrated circuit chips are less than a second distance between a top surface of said placement guide and said bottom surface of said placement guide, said first and second distances measured perpendicular to said top surface of said module substrate.
15. The method of claim 1 , wherein first distances from said top surface of said module substrate to respective top surfaces of each integrated circuit chip of said one or more integrated circuit chips are greater than a second distance between a top surface of said placement guide and said bottom surface of said placement guide, said first and second distances measured perpendicular to said top surface of said module substrate.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 15, 2007
November 10, 2009
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