Integrated structures and fabrication methods thereof implementing a cell phone or other electronic system

1. An electronic module comprising: a chip layer including: at least one chip, each chip comprising at least one side surface, an upper surface, a lower surface, and at least one contact pad at the upper surface; a structural material surrounding and physically contacting the at least one side surface of each chip of the at least one chip of the chip layer, the structural material having an upper surface substantially co-planar with or parallel to an upper surface of each chip of the at least one chip and defining at least a portion of a front surface of the chip layer, and a lower surface substantially co-planar with or parallel to a lower surface of each chip of the at least one chip and defining at least a portion of a back surface of the chip layer; and a plurality of conductive structures extending through the structural material between the front surface and the back surface of the chip layer; an interconnect layer disposed over the front surface of the chip layer, the interconnect layer including at least one interconnect metallization electrically connected to one or more conductive structures of the plurality of conductive structures extending between the front surface and back surface of the chip layer, wherein the interconnect layer connects to a contact pad of the at least one contact pad of the at least one chip; a redistribution layer disposed over the back surface of the chip layer, the redistribution layer including at least one redistribution metallization electrically connected to the one or more conductive structures of the plurality of conductive structures extending between the front and back surface of the chip layer; and a plurality of input/output contacts disposed over the back surface of the chip layer, including over the lower surface of a chip of the at least one chip, and electrically connected through the at least one redistribution metallization, one or more conductive structures, to the at least one interconnect metallization over the at least one chip of the chip layer.

2. The electronic module of claim 1 , further comprising at least one device disposed above the interconnect layer over the front surface of the chip layer.

3. The electronic module of claim 2 , wherein the at least one device is electrically connected via, in part, at least one conductive structure of the plurality of conductive structures to at least one input/output contact of the plurality of input/output contacts arrayed over the redistribution layer over the back surface of the chip layer to facilitate electrical input/output connection thereto.

4. The electronic module of claim 3 , further comprising an encapsulant surrounding the at least one device disposed above the interconnect layer, and wherein the plurality of input/output contacts arrayed over the redistribution layer are the only electrical input/output pathways for the electronic module.

5. The electronic module of claim 2 , wherein the interconnect layer electrically interconnects the at least one device and the at least one chip of the chip layer.

6. The electronic module of claim 2 , wherein the plurality of input/output contacts arrayed over the redistribution layer over the back surface of the chip layer are the only electrical input/output pathways for the electronic module.

7. The electronic module of claim 2 , further comprising an encapsulant material surrounding the at least one device.

8. The electronic module of claim 7 , further comprising a stiffener disposed over the encapsulant surrounding the at least one device to provide rigidity to the electronic module, the stiffener comprising a material different from the encapsulant material.

9. The electronic module of claim 2 , wherein the at least one device is packaged and comprises at least one integrated circuit chip and input/output contacts on a surface thereof electrically connected to the at least one interconnect metallization disposed over the front surface of the chip layer.

10. The electronic module of claim 1 , further comprising a plurality of additional input/output contacts arrayed over the interconnect layer disposed over the front surface of the chip layer to facilitate stacking of a plurality of chip layers.

11. The electronic module of claim 10 , wherein one plurality of the plurality of input/output contacts arrayed over the redistribution layer and the plurality of additional input/output contacts arrayed over the interconnect layer comprises a plurality of electrical contact pads and the other plurality comprises a plurality of solder bumps.

12. The electronic module of claim 11 , further comprising multiple chip layers stacked and electrically interconnected via at least the plurality of input/output contact pads of one chip layer being electrically connected to the plurality of solder bumps of an adjacent chip layer.

13. The electronic module of claim 1 , wherein at least one of the interconnect layer and the redistribution layer comprises an in situ processed layer.

14. The electronic module of claim 1 , further comprising an encapsulant material over the interconnect layer disposed over the front surface of the chip layer.

15. The electronic module of claim 14 , further comprising a stiffener disposed over the encapsulant to provide rigidity to the electronic module, the stiffener comprising a material different from the encapsulant material.

16. The electronic module of claim 1 , wherein the redistribution layer further includes at least one strengthening metallization contacting the back surface of the chip layer, the at least one strengthening metallization strengthening at least one interface between the at least one chip and the structure material.

17. The electronic module of claim 1 , wherein the redistribution layer further includes at least one electrical connection of the lower surface of a chip of the at least one chip to at least one conductive structure of the plurality of conductive structures of the chip layer.

18. An electronic module comprising: a chip layer including: at least one chip, each chip comprising at least one side surface, an upper surface, a lower surface, and at least one contact pad at the upper surface; a structural material surrounding and physically contacting the at least one side surface of each chip of the chip layer, the structural material having an upper surface substantially co-planar with or parallel to an upper surface of each chip of the at least one chip and defining at least a portion of a front surface of the chip layer, and a lower surface substantially co-planar with or parallel to a lower surface of each chip of the at least one chip and defining at least a portion of a back surface of the chip layer; and a plurality of conductive structures extending through the structural material between the front surface and the back surface of the chip layer; an interconnect layer disposed over the front surface of the chip layer, the interconnect layer including at least one interconnect metallization electrically connected to one or more conductive structures of the plurality of conductive structures extending between the front surface and back surface of the chip layer; a redistribution layer disposed over the back surface of the chip layer, the redistribution layer including at least one redistribution metallization electrically connected to the one or more conductive structures of the plurality of conductive structures extending between the front and back surface of the chip layer; a plurality of input/output contacts disposed over the front surface of the chip layer, including over the upper surface of a chip of the at least one chip of the chip layer, wherein the interconnect layer electrically connects to the plurality of input/output contacts disposed over the front surface of the chip layer; and at least one device disposed over the redistribution layer over the back surface of the chip layer, wherein electrical connection is made to the at least one device via, in part, at least one conductive structure of the plurality of conductive structures extending through the structural material between the front surface and the back surface of the chip layer.

19. The electronic module of claim 18 , wherein electrical connection to the at least one device is through the at least one redistribution metallization, and the at least one conductive structure of the plurality of conductive structures, to the at least one interconnect metallization.

20. The electronic module of claim 19 , further comprising an encapsulant material surrounding the at least one additional chip disposed over the redistribution layer over the back surface of the chip layer.

21. The electronic module of claim 20 , further comprising a stiffener disposed over the encapsulant material to provide rigidity to the chip module, the stiffener comprising a material different from the encapsulant material.

22. A method of fabricating an electronic module comprising: forming a chip layer including: obtaining at least one chip, each chip comprising at least one side surface, an upper surface, a lower surface, and at least one contact pad at the upper surface; disposing a structural material around and physically contacting the at least one side surface of each chip of the at least one chip of the chip layer, the structural material having an upper surface substantially co-planar with or parallel to an upper surface of each chip of the at least one chip and defining at least a portion of a front surface of the chip layer, and a lower surface substantially co-planar with or parallel to a lower surface of each chip of the at least one chip and defining at least a portion of a back surface of the chip layer; and providing a plurality of conductive structures extending through the structural material between the front surface and the back surface of the chip layer; disposing an interconnect layer over the front surface of the chip layer, the interconnect layer including at least one interconnect metallization electrically connected to one or more conductive structures of the plurality of conductive structures extending between the front surface and back surface of the chip layer, wherein the interconnect layer connects to a contact pad of the at least one contact pad of the at least one chip; disposing a redistribution layer over the back surface of the chip layer, the redistribution layer including at least one redistribution metallization electrically connected to the one or more conductive structures of the plurality of conductive structures extending between the front and back surface of the chip layer; and providing a plurality of input/output contacts disposed over the back surface of the chip layer, including over the lower surface of the at least one chip and electrically connected through the at least one redistribution metallization, one or more conductive structures, to the at least one interconnect metallization over the at least one chip of the chip layer.

23. The method of claim 22 , wherein the plurality of input/output contacts arrayed over the back surface of the chip layer is a first plurality of input/output contacts, and wherein the method further comprises: providing a second plurality of input/output contacts disposed over the front surface of the chip layer to facilitate electrical interconnection and stacking of a plurality of chip layers, the second plurality of input/output contacts being electrically connected to the at least one interconnect metallization.

24. A method of fabricating an electronic module comprising: forming a chip layer including: obtaining at least one chip, each chip comprising at least one side surface, an upper surface, a lower surface, and at least one contact pad at the upper surface; disposing a structural material around and physically contacting the at least one side surface of each chip of the chip layer, the structural material having an upper surface substantially co-planar with or parallel to an upper surface of each chip of the at least one chip and defining at least a portion of a front surface of the chip layer, and a lower surface substantially co-planar with or parallel to a lower surface of each chip of the at least one chip and defining at least a portion of a back surface of the chip layer; and providing a plurality of conductive structures extending through the structural material between the front surface and the back surface of the chip layer; disposing an interconnect layer over the front surface of the chip layer, the interconnect layer including at least one interconnect metallization electrically connected to one or more conductive structures of the plurality of conductive structures extending between the front surface and back surface of the chip layer, wherein the interconnect layer connects to a contact pad of the at least one contact pad of the at least one chip; disposing a redistribution layer over the back surface of the chip layer, the redistribution layer including at least one redistribution metallization electrically connected to the one or more conductive structures of the plurality of conductive structures extending between the front and back surface of the chip layer; providing a plurality of input/output contacts arrayed over the front surface of the chip layer, including over the upper surface of at least one chip of the chip layer; and disposing at least one device over the redistribution layer over the back surface of the chip layer, wherein electrical connection is made to the at least one device via, in part, at least one conductive structure of the plurality of conductive structures extending through the structural material between the front surface and the back surface of the chip layer.