System for programming a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline by injecting hot carriers from a drain region of an injecting memory cell having a gate node coupled to a next neighbor wordline WL(n−1) into a floating gate of the selected non-volatile memory cell on the wordline WL(n).
Legal claims defining the scope of protection, as filed with the USPTO.
1. A system for providing low voltage programming of a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline, comprising: a programming module; an interface arranged to electrically couple the memory array to the programming module; and a processor included in the programming module and electrically coupled to the interface to execute programming instructions: (a) causing hot carriers to be injected from a drain region of an injecting memory cell having a gate node coupled to a next neighbor wordline WL(n−1) into a floating gate of the selected non-volatile memory cell on the wordline WL(n).
2. A system as recited in claim 1 , wherein the programming instructions include computer code executable by the processor for: (b) determining a threshold voltage of the selected non-volatile memory cell; and (c) locking out the non-volatile memory cell if the threshold voltage is greater than an target threshold voltage.
3. A system as recited in claim 2 wherein the programming instructions further include computer code executable by the processor for, holding the selected bitline at ground; applying V dd to all unselected bitlines; applying low passing voltage V passL to a drain select gate (SGD) line; applying V pp to common source line; applying a high passing voltage V passH to all unselected wordlines except for the next neighbor word line WL(n−1); applying the high passing voltage V passH to a source gate select (SGS) line; applying V pgm to the selected word line WL(n); and sweeping a next neighbor word line WL(n−1) gate node voltage from about 0 V to about a V read , when the threshold voltage is less than the target voltage.
4. A system as recited in claim 3 , wherein the programming instructions further include computer code executable by the processor for: incrementing the program voltage V pgm and the V passH and V passL voltages; and returning to determining (b).
5. A system as recited in claim 3 , wherein V pgm ranges from about 8V to about 14V, V passL ranges from about 4V to about 10V, V passH ranges from about 5V to about 10V, V pp ranges from about 3.5V to about 5.5V, and V dd ranges from about 1.8V to about 3.6V.
6. A system as recited in claim 2 wherein the programming instructions further include computer code executable by the processor for, holding the selected bitline at V pp ; grounding to all unselected bitlines; applying high passing voltage V passH to a drain select gate (SGD) line and unselected wordlines except for the next neighbor wordline WL(n−1); applying low passing voltage V passL to SGS line; grounding common source line; applying V pgm to the selected word line WL(n); and sweeping a next neighbor word line WL(n−1) gate node voltage from about 0 V to about a V read when the threshold voltage is less than the target voltage.
7. A system as recited in claim 5 , wherein the programming instructions further include computer code executable by the processor for, incrementing the program voltage Vpgm and the VpassH and VpassL voltages; and returning to determining (b).
8. A system as recited in claim 6 , wherein V pgm ranges from about 8V to about 14V, V passL ranges from about 4V to about 10V, V passH ranges from about 5V to about 10V, V pp ranges from about 3.5V to about 5.5V, and V dd ranges from about 1.8V to about 3.6V.
9. A low voltage method as recited in claim 1 , wherein the memory array is a NAND type memory array.
10. A system for providing low voltage programming of a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline, comprising: a programming module; an interface arranged to electrically couple the memory array to the programming module; and a processor included in the programming module and electrically coupled to the interface to execute programming instructions only if a threshold voltage of the selected non-volatile memory cell is less than a target threshold voltage where the programming instructions include holding the selected bitline at ground, applying V dd to all unselected bitlines; applying low passing voltage V passL to a drain select gate (SGD) line, applying V pp to common source line, applying a high passing voltage V passH to all unselected wordlines except for the next neighbor word line WL(n−1), applying the high passing voltage V passH to a source gate select (SGS) line, applying V pgm to the selected word line WL(n), and sweeping a next neighbor word line WL(n−1) gate node voltage from about 0 V to about a V read thereby causing hot carriers to be injected from a drain region of an injecting memory cell having a gate node coupled to a next neighbor wordline WL(n−1) into a floating gate of the selected non-volatile memory cell on the wordline WL(n), otherwise, if the threshold voltage is greater than a target threshold voltage, the non-volatile memory cell is locked out.
11. A system as recited in claim 10 , wherein the programming instructions further include incrementing the program voltage V pgm and the V passH and V passL voltages, and continuing the programming of the non-volatile memory cell if the threshold voltage is less than the target threshold voltage.
12. A system as recited in claim 11 , wherein V pgm ranges from about 8V to about 14V, V passL ranges from about 4V to about 10V, V passH ranges from about 5V to about 10V, V pp ranges from about 3.5V to about 5.5V, and V dd ranges from about 1.8V to about 3.6V.
13. A system as recited in claim 10 , wherein the memory array is a NAND type memory array.
14. A system for providing low voltage programming of a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline, comprising: a programming module; an interface arranged to electrically couple the memory array to the programming module; and a processor included in the programming module and electrically coupled to the interface to execute programming instructions only if a threshold voltage of the selected non-volatile memory cell is less than a target threshold voltage, where the programming instructions include holding the selected bitline at V pp , grounding to all unselected bitlines, applying high passing voltage VpassH to a drain select gate (SGD) line and unselected wordlines except for the next neighbor wordline WL(n−1), applying low passing voltage V passL to SGS line; grounding common source line, applying V pgm to the selected word line WL(n), and sweeping a next neighbor word line WL(n−1) gate node voltage from about 0 V to about a V read when the threshold voltage is less than the target voltage thereby causing hot carriers to be injected from a drain region of an injecting memory cell having a gate node coupled to a next neighbor wordline WL(n−1) into a floating gate of the selected non-volatile memory cell on the wordline WL(n), otherwise, if the threshold voltage is greater than an target threshold voltage, the non-volatile memory cell is locked out.
15. A system as recited in claim 14 , wherein the programming instructions further include incrementing the program voltage V pgm and the V passH and V passL voltages, and continuing the programming of the non-volatile memory cell if the threshold voltage is less than the target threshold voltage.
16. A system as recited in claim 15 , wherein V pgm ranges from about 8V to about 14V, V passL ranges from about 4V to about 10V, V passH ranges from about 5V to about 10V, V pp ranges from about 3.5V to about 5.5V, and V dd ranges from about 1.8V to about 3.6V.
17. A system as recited in claim 14 , wherein the memory array is a NAND type memory array.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 21, 2006
November 24, 2009
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